Lines Matching full:rcc
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
264 clocks = <&rcc 1 CLK_USART2>;
272 clocks = <&rcc 1 CLK_USART3>;
280 clocks = <&rcc 1 CLK_UART4>;
288 clocks = <&rcc 1 CLK_UART5>;
297 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
298 clocks = <&rcc 1 CLK_I2C1>;
309 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
310 clocks = <&rcc 1 CLK_I2C2>;
321 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
322 clocks = <&rcc 1 CLK_I2C3>;
333 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
334 clocks = <&rcc 1 CLK_I2C4>;
344 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
353 clocks = <&rcc 1 CLK_UART7>;
361 clocks = <&rcc 1 CLK_UART8>;
370 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
392 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
413 clocks = <&rcc 1 CLK_USART1>;
421 clocks = <&rcc 1 CLK_USART6>;
429 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
440 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
465 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
485 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
499 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
518 clocks = <&rcc 0 12>;
522 rcc: rcc@40023800 { label
525 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
529 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
544 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
560 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
570 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
582 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
590 clocks = <&rcc 1 0>;