Lines Matching +full:0 +full:x40002000
53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
124 #size-cells = <0>;
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
146 #size-cells = <0>;
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
168 #size-cells = <0>;
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
184 #size-cells = <0>;
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
200 #size-cells = <0>;
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
250 reg = <0x40002800 0x400>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
262 reg = <0x40004400 0x400>;
270 reg = <0x40004800 0x400>;
278 reg = <0x40004c00 0x400>;
286 reg = <0x40005000 0x400>;
294 reg = <0x40005400 0x400>;
300 #size-cells = <0>;
306 reg = <0x40005800 0x400>;
312 #size-cells = <0>;
318 reg = <0x40005c00 0x400>;
324 #size-cells = <0>;
330 reg = <0x40006000 0x400>;
336 #size-cells = <0>;
342 reg = <0x40006C00 0x400>;
344 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
351 reg = <0x40007800 0x400>;
359 reg = <0x40007c00 0x400>;
367 #size-cells = <0>;
369 reg = <0x40010000 0x400>;
370 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
380 timer@0 {
382 reg = <0>;
389 #size-cells = <0>;
391 reg = <0x40010400 0x400>;
392 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
411 reg = <0x40011000 0x400>;
419 reg = <0x40011400 0x400>;
427 arm,primecell-periphid = <0x00880180>;
428 reg = <0x40011c00 0x400>;
429 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
438 arm,primecell-periphid = <0x00880180>;
439 reg = <0x40012c00 0x400>;
440 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
449 reg = <0x40013800 0x400>;
456 reg = <0x40013C00 0x400>;
462 #size-cells = <0>;
464 reg = <0x40014000 0x400>;
465 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
484 reg = <0x40014400 0x400>;
485 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
498 reg = <0x40014800 0x400>;
499 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
512 reg = <0x40007000 0x400>;
517 reg = <0x40023000 0x400>;
518 clocks = <&rcc 0 12>;
526 reg = <0x40023800 0x400>;
535 reg = <0x40026000 0x400>;
544 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
551 reg = <0x40026400 0x400>;
560 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
568 reg = <0x40040000 0x40000>;
570 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
580 reg = <0x50000000 0x40000>;
582 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
590 clocks = <&rcc 1 0>;