Lines Matching +full:0 +full:x40028000
58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
100 reg = <0x40000000 0x400>;
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
120 #size-cells = <0>;
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
142 #size-cells = <0>;
144 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
164 #size-cells = <0>;
166 reg = <0x40000C00 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
186 #size-cells = <0>;
188 reg = <0x40001000 0x400>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
202 #size-cells = <0>;
204 reg = <0x40001400 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
218 #size-cells = <0>;
220 reg = <0x40001800 0x400>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
240 reg = <0x40001C00 0x400>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
254 reg = <0x40002000 0x400>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
268 reg = <0x40002800 0x400>;
274 st,syscfg = <&pwrcfg 0x00 0x100>;
280 reg = <0x40003000 0x400>;
288 #size-cells = <0>;
290 reg = <0x40003800 0x400>;
292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
298 #size-cells = <0>;
300 reg = <0x40003c00 0x400>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
308 reg = <0x40004400 0x400>;
310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
316 reg = <0x40004800 0x400>;
318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
320 dmas = <&dma1 1 4 0x400 0x0>,
321 <&dma1 3 4 0x400 0x0>;
327 reg = <0x40004c00 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
335 reg = <0x40005000 0x400>;
337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
343 reg = <0x40005400 0x400>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
349 #size-cells = <0>;
355 reg = <0x40005c00 0x400>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
361 #size-cells = <0>;
367 reg = <0x40007400 0x400>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
372 #size-cells = <0>;
392 reg = <0x40007800 0x400>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
400 reg = <0x40007c00 0x400>;
402 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
408 #size-cells = <0>;
410 reg = <0x40010000 0x400>;
411 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
421 timer@0 {
423 reg = <0>;
430 #size-cells = <0>;
432 reg = <0x40010400 0x400>;
433 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
452 reg = <0x40011000 0x400>;
454 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
456 dmas = <&dma2 2 4 0x400 0x0>,
457 <&dma2 7 4 0x400 0x0>;
463 reg = <0x40011400 0x400>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
471 reg = <0x40012000 0x400>;
473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
478 #size-cells = <0>;
481 adc1: adc@0 {
484 reg = <0x0>;
485 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
487 interrupts = <0>;
488 dmas = <&dma2 0 0 0x400 0x0>;
496 reg = <0x100>;
497 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
500 dmas = <&dma2 3 1 0x400 0x0>;
508 reg = <0x200>;
509 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
512 dmas = <&dma2 1 2 0x400 0x0>;
520 arm,primecell-periphid = <0x00880180>;
521 reg = <0x40012c00 0x400>;
522 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
531 #size-cells = <0>;
533 reg = <0x40013000 0x400>;
535 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
541 #size-cells = <0>;
543 reg = <0x40013400 0x400>;
545 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
551 reg = <0x40013800 0x400>;
558 reg = <0x40013C00 0x400>;
564 #size-cells = <0>;
566 reg = <0x40014000 0x400>;
567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
586 reg = <0x40014400 0x400>;
587 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
600 reg = <0x40014800 0x400>;
601 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
614 #size-cells = <0>;
616 reg = <0x40015000 0x400>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
619 dmas = <&dma2 3 2 0x400 0x0>,
620 <&dma2 4 2 0x400 0x0>;
627 #size-cells = <0>;
629 reg = <0x40015400 0x400>;
631 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
637 reg = <0x40007000 0x400>;
642 reg = <0x40016800 0x200>;
652 reg = <0x40023000 0x400>;
653 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
661 reg = <0x40023800 0x400>;
670 reg = <0x40026000 0x400>;
679 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
685 reg = <0x40026400 0x400>;
694 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
701 reg = <0x40028000 0x8000>;
706 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
707 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
708 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
709 st,syscon = <&syscfg 0x4>;
717 reg = <0x4002b000 0xc00>;
720 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
727 reg = <0x40040000 0x40000>;
729 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
736 reg = <0x50000000 0x40000>;
738 clocks = <&rcc 0 39>;
745 reg = <0x50050000 0x400>;
748 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
751 pinctrl-0 = <&dcmi_pins>;
752 dmas = <&dma2 1 1 0x414 0x3>;
759 reg = <0x50060800 0x400>;
760 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;