Lines Matching +full:0 +full:x80004000
39 #size-cells = <0>;
55 reg = <0x300>;
64 reg = <0x301>;
80 polling-delay = <0>;
92 hysteresis = <0>;
114 reg = <0x801ae000 0x1000>;
130 reg = <0x801af000 0x1000>;
146 reg = <0x801a6000 0x1000>;
161 #size-cells = <0>;
163 port@0 {
164 reg = <0>;
186 #size-cells = <0>;
188 port@0 {
189 reg = <0>;
213 reg = <0x80190000 0x1000>;
228 reg = <0x801a4000 0x1000>;
246 reg = <0xa0411000 0x1000>,
247 <0xa0410100 0x100>;
252 reg = <0xa0410000 0x100>;
261 reg = <0x80150000 0x2000>;
266 reg = <0xa0412000 0x1000>;
288 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
289 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
290 <0xa03cf000 0x1000>;
309 #clock-cells = <0>;
313 #clock-cells = <0>;
320 reg = <0xa03c6000 0x1000>;
329 reg = <0xa0410600 0x20>;
337 reg = <0xa0410620 0x20>;
344 reg = <0x80154000 0x1000>;
354 reg = <0x8012e000 0x80>;
361 gpio-bank = <0>;
362 gpio-ranges = <&pinctrl 0 0 32>;
369 reg = <0x8012e080 0x80>;
377 gpio-ranges = <&pinctrl 0 32 5>;
384 reg = <0x8000e000 0x80>;
392 gpio-ranges = <&pinctrl 0 64 32>;
399 reg = <0x8000e080 0x80>;
407 gpio-ranges = <&pinctrl 0 96 2>;
414 reg = <0x8000e100 0x80>;
422 gpio-ranges = <&pinctrl 0 128 32>;
429 reg = <0x8000e180 0x80>;
437 gpio-ranges = <&pinctrl 0 160 12>;
444 reg = <0x8011e000 0x80>;
452 gpio-ranges = <&pinctrl 0 192 32>;
459 reg = <0x8011e080 0x80>;
467 gpio-ranges = <&pinctrl 0 224 7>;
474 reg = <0xa03fe000 0x80>;
482 gpio-ranges = <&pinctrl 0 256 12>;
496 reg = <0xa03e0000 0x10000>;
502 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
503 <&dma 38 0 0x0>, /* Logical - MemToDev */
504 <&dma 37 0 0x2>, /* Logical - DevToMem */
505 <&dma 37 0 0x0>, /* Logical - MemToDev */
506 <&dma 36 0 0x2>, /* Logical - DevToMem */
507 <&dma 36 0 0x0>, /* Logical - MemToDev */
508 <&dma 19 0 0x2>, /* Logical - DevToMem */
509 <&dma 19 0 0x0>, /* Logical - MemToDev */
510 <&dma 18 0 0x2>, /* Logical - DevToMem */
511 <&dma 18 0 0x0>, /* Logical - MemToDev */
512 <&dma 17 0 0x2>, /* Logical - DevToMem */
513 <&dma 17 0 0x0>, /* Logical - MemToDev */
514 <&dma 16 0 0x2>, /* Logical - DevToMem */
515 <&dma 16 0 0x0>, /* Logical - MemToDev */
516 <&dma 39 0 0x2>, /* Logical - DevToMem */
517 <&dma 39 0 0x0>; /* Logical - MemToDev */
528 clocks = <&prcc_pclk 5 0>;
533 reg = <0x801C0000 0x1000 0x40010000 0x800>;
545 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
556 reg = <0x80157450 0xC>;
561 reg = <0x801573c0 0x40>;
566 #thermal-sensor-cells = <0>;
659 reg = <0x80004000 0x1000>;
663 #size-cells = <0>;
676 reg = <0x80122000 0x1000>;
680 #size-cells = <0>;
694 reg = <0x80128000 0x1000>;
698 #size-cells = <0>;
712 reg = <0x80110000 0x1000>;
716 #size-cells = <0>;
720 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
730 reg = <0x8012a000 0x1000>;
734 #size-cells = <0>;
748 reg = <0x80002000 0x1000>;
751 #size-cells = <0>;
754 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
755 <&dma 8 0 0x0>; /* Logical - MemToDev */
765 reg = <0x80003000 0x1000>;
768 #size-cells = <0>;
771 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
772 <&dma 9 0 0x0>; /* Logical - MemToDev */
782 reg = <0x8011a000 0x1000>;
785 #size-cells = <0>;
789 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
790 <&dma 0 0 0x0>; /* Logical - MemToDev */
799 reg = <0x80112000 0x1000>;
802 #size-cells = <0>;
806 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
807 <&dma 35 0 0x0>; /* Logical - MemToDev */
816 reg = <0x80111000 0x1000>;
819 #size-cells = <0>;
823 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
824 <&dma 33 0 0x0>; /* Logical - MemToDev */
833 reg = <0x80129000 0x1000>;
836 #size-cells = <0>;
840 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
841 <&dma 40 0 0x0>; /* Logical - MemToDev */
851 reg = <0x80120000 0x1000>;
854 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
855 <&dma 13 0 0x0>; /* Logical - MemToDev */
858 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
867 reg = <0x80121000 0x1000>;
870 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
871 <&dma 12 0 0x0>; /* Logical - MemToDev */
883 reg = <0x80007000 0x1000>;
886 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
887 <&dma 11 0 0x0>; /* Logical - MemToDev */
899 reg = <0x80126000 0x1000>;
902 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
903 <&dma 29 0 0x0>; /* Logical - MemToDev */
916 reg = <0x80118000 0x1000>;
919 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
920 <&dma 32 0 0x0>; /* Logical - MemToDev */
933 reg = <0x80005000 0x1000>;
936 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
937 <&dma 28 0 0x0>; /* Logical - MemToDev */
950 reg = <0x80119000 0x1000>;
953 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
954 <&dma 41 0 0x0>; /* Logical - MemToDev */
967 reg = <0x80114000 0x1000>;
970 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
971 <&dma 42 0 0x0>; /* Logical - MemToDev */
984 reg = <0x80008000 0x1000>;
987 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
988 <&dma 43 0 0x0>; /* Logical - MemToDev */
1006 reg = <0x80123000 0x1000>;
1010 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1011 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1023 reg = <0x80124000 0x1000>;
1028 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1041 reg = <0x80117000 0x1000>;
1045 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1046 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1059 reg = <0x80125000 0x1000>;
1064 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1076 reg = <0x50000000 0x4000000>;
1079 ranges = <0 0x50000000 0x4000000>;
1090 reg = <0xa0300000 0x10000>;
1109 reg = <0xa0350000 0x1000>;
1123 reg = <0xa0351000 0x1000>;
1127 #size-cells = <0>;
1131 reg = <0xa0352000 0x1000>;
1135 #size-cells = <0>;
1139 reg = <0xa0353000 0x1000>;
1144 #size-cells = <0>;
1150 reg = <0xa03cb000 0x1000>;
1159 reg = <0xa03c2000 0x1000>;