Lines Matching +full:0 +full:xfc048000
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
46 reg = <0x740000 0x1000>;
62 reg = <0x73c000 0x1000>;
78 reg = <0x20000000 0x20000000>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
90 #clock-cells = <0>;
91 clock-frequency = <0>;
97 reg = <0x00200000 0x20000>;
100 ranges = <0 0x00200000 0x20000>;
122 reg = <0x00100000 0x2400>;
125 ranges = <0 0x00100000 0x2400>;
131 reg = <0x00300000 0x100000
132 0xfc02c000 0x400>;
141 reg = <0x00400000 0x100000>;
150 reg = <0x00500000 0x100000>;
159 reg = <0x00a00000 0x1000>;
170 reg = <0x10000000 0x10000000
171 0x60000000 0x30000000>;
172 ranges = <0x0 0x0 0x10000000 0x10000000
173 0x1 0x0 0x60000000 0x10000000
174 0x2 0x0 0x70000000 0x10000000
175 0x3 0x0 0x80000000 0x10000000>;
193 reg = <0xa0000000 0x300>;
194 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
204 reg = <0xb0000000 0x300>;
205 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
215 reg = <0xc0000000 0x8000000>;
226 reg = <0xf0000000 0x2000>;
227 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
235 #size-cells = <0>;
237 port@0 {
239 #size-cells = <0>;
240 reg = <0>;
252 reg = <0xf0008000 0x4000>;
256 #clock-cells = <0>;
263 reg = <0xf000c000 0x200>;
270 reg = <0xf0010000 0x1000>;
271 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
280 reg = <0xf0004000 0x1000>;
281 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
289 reg = <0xf0014000 0x160>;
298 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
304 #size-cells = <0>;
310 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
316 #size-cells = <0>;
322 reg = <0xf0028000 0x100>;
323 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
334 reg = <0xf002c000 0x100>;
335 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
349 reg = <0xf8000000 0x100>;
352 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
355 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
362 #size-cells = <0>;
368 reg = <0xf8004000 0x4000>;
371 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
374 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
384 reg = <0xf8008000 0x1000>;
385 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
396 #size-cells = <0>;
397 reg = <0xf800c000 0x100>;
398 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
406 #size-cells = <0>;
407 reg = <0xf8010000 0x100>;
408 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
415 reg = <0xf8014000 0x1000>;
424 reg = <0xf8014070 0x490>,
425 <0xf8014500 0x200>;
431 reg = <0xf8018000 0x124>;
434 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
444 reg = <0xf801c000 0x100>;
448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
461 reg = <0xf8020000 0x100>;
465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
468 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
478 reg = <0xf8024000 0x100>;
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
495 reg = <0xf8028000 0x100>;
498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
499 AT91_XDMAC_DT_PERID(0))>,
501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
505 #size-cells = <0>;
513 reg = <0xf802c000 0x4000>;
522 reg = <0xf8030000 0x98>;
527 reg = <0xf8034000 0x200>;
531 ranges = <0x0 0xf8034000 0x800>;
536 reg = <0x200 0x200>;
542 (AT91_XDMAC_DT_MEM_IF(0) |
546 (AT91_XDMAC_DT_MEM_IF(0) |
556 reg = <0x400 0x200>;
559 #size-cells = <0>;
563 (AT91_XDMAC_DT_MEM_IF(0) |
567 (AT91_XDMAC_DT_MEM_IF(0) |
577 reg = <0x600 0x200>;
580 #size-cells = <0>;
583 (AT91_XDMAC_DT_MEM_IF(0) |
587 (AT91_XDMAC_DT_MEM_IF(0) |
598 reg = <0xf8038000 0x200>;
602 ranges = <0x0 0xf8038000 0x800>;
607 reg = <0x200 0x200>;
613 (AT91_XDMAC_DT_MEM_IF(0) |
617 (AT91_XDMAC_DT_MEM_IF(0) |
627 reg = <0x400 0x200>;
630 #size-cells = <0>;
634 (AT91_XDMAC_DT_MEM_IF(0) |
638 (AT91_XDMAC_DT_MEM_IF(0) |
648 reg = <0x600 0x200>;
651 #size-cells = <0>;
654 (AT91_XDMAC_DT_MEM_IF(0) |
658 (AT91_XDMAC_DT_MEM_IF(0) |
669 reg = <0xf8044000 0x1420>;
674 ranges = <0 0xf8044000 0x1420>;
679 reg = <0xf8048000 0x10>;
685 reg = <0xf8048010 0x10>;
688 #size-cells = <0>;
694 reg = <0xf8048030 0x10>;
701 reg = <0xf8048040 0x10>;
709 reg = <0xf8048050 0x4>;
712 #clock-cells = <0>;
717 reg = <0xf80480b0 0x30>;
724 reg = <0xf8050000 0x100>;
727 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
730 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
742 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
752 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
758 reg = <0xfc000000 0x100>;
761 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
764 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
771 #size-cells = <0>;
777 reg = <0xfc008000 0x100>;
781 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
784 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
794 reg = <0xfc00c000 0x100>;
797 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
800 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
811 reg = <0xfc010000 0x200>;
815 ranges = <0x0 0xfc010000 0x800>;
820 reg = <0x200 0x200>;
826 (AT91_XDMAC_DT_MEM_IF(0) |
830 (AT91_XDMAC_DT_MEM_IF(0) |
840 reg = <0x400 0x200>;
843 #size-cells = <0>;
847 (AT91_XDMAC_DT_MEM_IF(0) |
851 (AT91_XDMAC_DT_MEM_IF(0) |
861 reg = <0x600 0x200>;
864 #size-cells = <0>;
867 (AT91_XDMAC_DT_MEM_IF(0) |
871 (AT91_XDMAC_DT_MEM_IF(0) |
882 reg = <0xfc014000 0x200>;
886 ranges = <0x0 0xfc014000 0x800>;
891 reg = <0x200 0x200>;
897 (AT91_XDMAC_DT_MEM_IF(0) |
901 (AT91_XDMAC_DT_MEM_IF(0) |
911 reg = <0x400 0x200>;
914 #size-cells = <0>;
918 (AT91_XDMAC_DT_MEM_IF(0) |
922 (AT91_XDMAC_DT_MEM_IF(0) |
932 reg = <0x600 0x200>;
935 #size-cells = <0>;
938 (AT91_XDMAC_DT_MEM_IF(0) |
942 (AT91_XDMAC_DT_MEM_IF(0) |
954 reg = <0xfc018000 0x200>;
958 ranges = <0x0 0xfc018000 0x800>;
963 reg = <0x200 0x200>;
969 (AT91_XDMAC_DT_MEM_IF(0) |
973 (AT91_XDMAC_DT_MEM_IF(0) |
983 reg = <0x400 0x200>;
986 #size-cells = <0>;
990 (AT91_XDMAC_DT_MEM_IF(0) |
994 (AT91_XDMAC_DT_MEM_IF(0) |
1004 reg = <0x600 0x200>;
1007 #size-cells = <0>;
1010 (AT91_XDMAC_DT_MEM_IF(0) |
1014 (AT91_XDMAC_DT_MEM_IF(0) |
1025 reg = <0xfc01c000 0x100>;
1026 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1034 reg = <0xfc020000 0x200>;
1040 reg = <0xfc028000 0x100>;
1043 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1046 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1050 #size-cells = <0>;
1058 reg = <0xfc030000 0x100>;
1062 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1074 reg = <0xfc038000 0x600>;
1088 reg = <0xfc040000 0x100>;
1096 reg = <0xfc044000 0x100>;
1097 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1099 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1102 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1111 reg = <0xfc048000 0x100>;
1114 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1124 reg = <0xfc04c000 0x100>;
1127 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1142 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1152 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1158 reg = <0xfc05c000 0x20>;
1163 reg = <0xfc069000 0x8>;