Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
39 cpu@0 {
40 compatible = "arm,arm926ej-s";
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x100000>;
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchip,sam9x60-udc";
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
85 clock-names = "pclk", "hclk";
86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87 assigned-clock-rates = <480000000>;
92 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93 reg = <0x00600000 0x100000>;
96 clock-names = "ohci_clk", "hclk", "uhpck";
101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102 reg = <0x00700000 0x100000>;
105 clock-names = "usb_clk", "ehci_clk";
106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107 assigned-clock-rates = <480000000>;
112 compatible = "microchip,sam9x60-ebi";
113 #address-cells = <2>;
114 #size-cells = <1>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
127 nand_controller: nand-controller {
128 compatible = "microchip,sam9x60-nand-controller";
129 ecc-engine = <&pmecc>;
130 #address-cells = <2>;
131 #size-cells = <1>;
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchip,sam9x60-sdhci";
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
142 clock-names = "hclock", "multclk";
143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144 assigned-clock-rates = <100000000>;
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchip,sam9x60-sdhci";
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
153 clock-names = "hclock", "multclk";
154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155 assigned-clock-rates = <100000000>;
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xf0000000 0x200>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xf0000000 0x800>;
176 compatible = "atmel,sama5d2-flexcom";
177 reg = <0xf0004000 0x200>;
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges = <0x0 0xf0004000 0x800>;
185 dma0: dma-controller@f0008000 {
186 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
187 reg = <0xf0008000 0x1000>;
188 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
189 #dma-cells = <1>;
191 clock-names = "dma_clk";
195 compatible = "atmel,at91sam9g45-ssc";
196 reg = <0xf0010000 0x4000>;
199 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
202 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
204 dma-names = "tx", "rx";
206 clock-names = "pclk";
211 compatible = "microchip,sam9x60-qspi";
212 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
213 reg-names = "qspi_base", "qspi_mmap";
216 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
219 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
221 dma-names = "tx", "rx";
223 clock-names = "pclk", "qspick";
225 #address-cells = <1>;
226 #size-cells = <0>;
231 compatible = "microchip,sam9x60-i2smcc";
232 reg = <0xf001c000 0x100>;
235 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
240 dma-names = "tx", "rx";
242 clock-names = "pclk", "gclk";
247 compatible = "atmel,sama5d2-flexcom";
248 reg = <0xf0020000 0x200>;
250 #address-cells = <1>;
251 #size-cells = <1>;
252 ranges = <0x0 0xf0020000 0x800>;
257 compatible = "atmel,sama5d2-flexcom";
258 reg = <0xf0024000 0x200>;
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0x0 0xf0024000 0x800>;
267 compatible = "microchip,sam9x60-pit64b";
268 reg = <0xf0028000 0x100>;
271 clock-names = "pclk", "gclk";
275 compatible = "atmel,at91sam9g46-sha";
276 reg = <0xf002c000 0x100>;
277 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
281 dma-names = "tx";
283 clock-names = "sha_clk";
287 compatible = "microchip,sam9x60-trng";
288 reg = <0xf0030000 0x100>;
289 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
294 compatible = "atmel,at91sam9g46-aes";
295 reg = <0xf0034000 0x100>;
296 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
298 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
301 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
303 dma-names = "tx", "rx";
305 clock-names = "aes_clk";
309 compatible = "atmel,at91sam9g46-tdes";
310 reg = <0xf0038000 0x100>;
311 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
313 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
316 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
318 dma-names = "tx", "rx";
320 clock-names = "tdes_clk";
324 compatible = "atmel,sama5d2-classd";
325 reg = <0xf003c000 0x100>;
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
330 dma-names = "tx";
332 clock-names = "pclk", "gclk";
337 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
338 reg = <0xf8000000 0x300>;
341 clock-names = "can_clk";
346 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
347 reg = <0xf8004000 0x300>;
350 clock-names = "can_clk";
355 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
356 #address-cells = <1>;
357 #size-cells = <0>;
358 reg = <0xf8008000 0x100>;
359 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
360 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
361 clock-names = "t0_clk", "slow_clk";
365 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <0xf800c000 0x100>;
369 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
371 clock-names = "t0_clk", "slow_clk";
375 compatible = "atmel,sama5d2-flexcom";
376 reg = <0xf8010000 0x200>;
378 #address-cells = <1>;
379 #size-cells = <1>;
380 ranges = <0x0 0xf8010000 0x800>;
385 compatible = "atmel,sama5d2-flexcom";
386 reg = <0xf8014000 0x200>;
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges = <0x0 0xf8014000 0x800>;
395 compatible = "atmel,sama5d2-flexcom";
396 reg = <0xf8018000 0x200>;
398 #address-cells = <1>;
399 #size-cells = <1>;
400 ranges = <0x0 0xf8018000 0x800>;
405 compatible = "atmel,sama5d2-flexcom";
406 reg = <0xf801c000 0x200>;
408 #address-cells = <1>;
409 #size-cells = <1>;
410 ranges = <0x0 0xf801c000 0x800>;
415 compatible = "atmel,sama5d2-flexcom";
416 reg = <0xf8020000 0x200>;
418 #address-cells = <1>;
419 #size-cells = <1>;
420 ranges = <0x0 0xf8020000 0x800>;
425 compatible = "atmel,sama5d2-flexcom";
426 reg = <0xf8024000 0x200>;
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0xf8024000 0x800>;
435 compatible = "atmel,sama5d2-flexcom";
436 reg = <0xf8028000 0x200>;
438 #address-cells = <1>;
439 #size-cells = <1>;
440 ranges = <0x0 0xf8028000 0x800>;
445 compatible = "cdns,sam9x60-macb", "cdns,macb";
446 reg = <0xf802c000 0x1000>;
449 clock-names = "hclk", "pclk";
454 compatible = "cdns,sam9x60-macb", "cdns,macb";
455 reg = <0xf8030000 0x1000>;
458 clock-names = "hclk", "pclk";
463 compatible = "microchip,sam9x60-pwm";
464 reg = <0xf8034000 0x300>;
467 #pwm-cells = <3>;
472 compatible = "microchip,sam9x60-hlcdc";
473 reg = <0xf8038000 0x4000>;
474 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
476 clock-names = "periph_clk","sys_clk", "slow_clk";
477 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
478 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
481 hlcdc-display-controller {
482 compatible = "atmel,hlcdc-display-controller";
483 #address-cells = <1>;
484 #size-cells = <0>;
486 port@0 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 reg = <0>;
493 hlcdc_pwm: hlcdc-pwm {
494 compatible = "atmel,hlcdc-pwm";
495 #pwm-cells = <3>;
500 compatible = "atmel,sama5d2-flexcom";
501 reg = <0xf8040000 0x200>;
503 #address-cells = <1>;
504 #size-cells = <1>;
505 ranges = <0x0 0xf8040000 0x800>;
510 compatible = "atmel,sama5d2-flexcom";
511 reg = <0xf8044000 0x200>;
513 #address-cells = <1>;
514 #size-cells = <1>;
515 ranges = <0x0 0xf8044000 0x800>;
520 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
521 reg = <0xf8048000 0x100>;
524 clock-names = "isi_clk";
527 #address-cells = <1>;
528 #size-cells = <0>;
533 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
534 reg = <0xf804c000 0x100>;
537 clock-names = "adc_clk";
538 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
539 dma-names = "rx";
540 atmel,min-sample-rate-hz = <200000>;
541 atmel,max-sample-rate-hz = <20000000>;
542 atmel,startup-time-ms = <4>;
543 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
544 #io-channel-cells = <1>;
549 compatible = "microchip,sam9x60-sfr", "syscon";
550 reg = <0xf8050000 0x100>;
554 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
555 reg = <0xffffde00 0x200>;
558 pmecc: ecc-engine@ffffe000 {
559 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
560 reg = <0xffffe000 0x300>,
561 <0xffffe600 0x100>;
565 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
566 reg = <0xffffe800 0x200>;
568 clock-names = "ddrck", "mpddr";
572 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
573 reg = <0xffffea00 0x100>;
576 aic: interrupt-controller@fffff100 {
577 compatible = "microchip,sam9x60-aic";
578 #interrupt-cells = <3>;
579 interrupt-controller;
580 reg = <0xfffff100 0x100>;
581 atmel,external-irqs = <31>;
585 …compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel…
586 reg = <0xfffff200 0x200>;
587 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
593 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
595 dma-names = "tx", "rx";
597 clock-names = "usart";
602 #address-cells = <1>;
603 #size-cells = <1>;
604 …compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", …
605 ranges = <0xfffff400 0xfffff400 0x800>;
607 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
608 atmel,mux-mask = <
610 0xffffffff 0xffe03fff 0xef00019d /* pioA */
611 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
612 0xffffffff 0xffffffff 0xf83fffff /* pioC */
613 0x003fffff 0x003f8000 0x00000000 /* pioD */
617 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
618 reg = <0xfffff400 0x200>;
620 #gpio-cells = <2>;
621 gpio-controller;
622 interrupt-controller;
623 #interrupt-cells = <2>;
628 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
629 reg = <0xfffff600 0x200>;
631 #gpio-cells = <2>;
632 gpio-controller;
633 #gpio-lines = <26>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
640 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
641 reg = <0xfffff800 0x200>;
643 #gpio-cells = <2>;
644 gpio-controller;
645 interrupt-controller;
646 #interrupt-cells = <2>;
651 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
652 reg = <0xfffffa00 0x200>;
654 #gpio-cells = <2>;
655 gpio-controller;
656 #gpio-lines = <22>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
664 compatible = "microchip,sam9x60-pmc", "syscon";
665 reg = <0xfffffc00 0x200>;
667 #clock-cells = <2>;
668 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
669 clock-names = "td_slck", "md_slck", "main_xtal";
672 reset_controller: reset-controller@fffffe00 {
673 compatible = "microchip,sam9x60-rstc";
674 reg = <0xfffffe00 0x10>;
675 clocks = <&clk32k 0>;
679 compatible = "microchip,sam9x60-shdwc";
680 reg = <0xfffffe10 0x10>;
681 clocks = <&clk32k 0>;
682 #address-cells = <1>;
683 #size-cells = <0>;
684 atmel,wakeup-rtc-timer;
685 atmel,wakeup-rtt-timer;
690 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
691 reg = <0xfffffe20 0x20>;
693 clocks = <&clk32k 0>;
697 compatible = "atmel,at91sam9260-pit";
698 reg = <0xfffffe40 0x10>;
704 compatible = "microchip,sam9x60-sckc";
705 reg = <0xfffffe50 0x4>;
707 #clock-cells = <1>;
711 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
712 reg = <0xfffffe60 0x10>;
716 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
717 reg = <0xfffffea8 0x100>;
719 clocks = <&clk32k 0>;
723 compatible = "microchip,sam9x60-wdt";
724 reg = <0xffffff80 0x24>;
726 clocks = <&clk32k 0>;