Lines Matching +full:0 +full:x10300000
29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
128 reg = <0x10230000 0x100>;
137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
143 reg = <0x10240000 0x1000>;
146 #size-cells = <0>;
150 pinctrl-0 = <&i2c1_xfer>;
157 reg = <0x10250000 0x1000>;
160 #size-cells = <0>;
164 pinctrl-0 = <&i2c2m1_xfer>;
171 reg = <0x10260000 0x1000>;
174 #size-cells = <0>;
178 pinctrl-0 = <&i2c3_xfer>;
185 reg = <0x10270000 0x1000>;
192 #size-cells = <0>;
198 reg = <0x10280000 0x10>;
203 pinctrl-0 = <&pwm4_pin>;
210 reg = <0x10280010 0x10>;
215 pinctrl-0 = <&pwm5_pin>;
222 reg = <0x10280020 0x10>;
227 pinctrl-0 = <&pwm6_pin>;
234 reg = <0x10280030 0x10>;
239 pinctrl-0 = <&pwm7_pin>;
246 reg = <0x102a0000 0x4000>;
247 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
257 reg = <0x10300000 0x1000>;
268 reg = <0x100 0x0c>;
271 #clock-cells = <0>;
279 #phy-cells = <0>;
286 #phy-cells = <0>;
294 reg = <0x10350000 0x20>;
302 reg = <0x10360000 0x100>;
313 thermal-sensors = <&tsadc 0>;
345 reg = <0x10370000 0x100>;
352 pinctrl-0 = <&otp_pin>;
364 reg = <0x1038c000 0x100>;
374 reg = <0x20000000 0x1000>;
377 #size-cells = <0>;
381 pinctrl-0 = <&i2c0_xfer>;
388 reg = <0x20040000 0x10>;
393 pinctrl-0 = <&pwm0_pin>;
400 reg = <0x20040010 0x10>;
405 pinctrl-0 = <&pwm1_pin>;
412 reg = <0x20040020 0x10>;
417 pinctrl-0 = <&pwm2_pin>;
424 reg = <0x20040030 0x10>;
429 pinctrl-0 = <&pwm3_pin>;
436 reg = <0x20060000 0x1000>;
446 reg = <0x202a0000 0x1000>;
451 reg = <0x20200000 0x1000>;
461 reg = <0x30100000 0x1000>;
472 reg = <0x30110000 0x4000>;
477 fifo-depth = <0x100>;
484 reg = <0x30120000 0x4000>;
489 fifo-depth = <0x100>;
496 reg = <0x30130000 0x4000>;
501 fifo-depth = <0x100>;
504 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
510 reg = <0x30140000 0x20000>;
520 reg = <0x30160000 0x20000>;
531 reg = <0x30180000 0x40000>;
546 reg = <0x301c0000 0x4000>;
550 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
557 reg = <0x30200000 0x10000>;
572 pinctrl-0 = <&rmii_pins>;
581 #address-cells = <0>;
583 reg = <0x32011000 0x1000>,
584 <0x32012000 0x2000>,
585 <0x32014000 0x2000>,
586 <0x32016000 0x2000>;
600 reg = <0x20030000 0x100>;
613 reg = <0x10310000 0x100>;
626 reg = <0x10320000 0x100>;
639 reg = <0x10330000 0x100>;
766 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
767 <0 RK_PB2 1 &pcfg_pull_none_smt>;
780 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
781 <0 RK_PC6 3 &pcfg_pull_none>;
785 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
786 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
804 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
805 <0 RK_PC4 2 &pcfg_pull_none>;
811 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
817 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
823 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
829 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
867 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
902 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
906 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
910 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
914 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
920 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
924 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;