Lines Matching +full:- +full:30200000
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
43 cpu_opp_table: opp-table-0 {
44 compatible = "operating-points-v2";
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
74 compatible = "arm,armv7-timer";
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
89 compatible = "mmio-sram";
91 #address-cells = <1>;
92 #size-cells = <1>;
97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
100 reg-shift = <2>;
101 reg-io-width = <4>;
102 clock-frequency = <24000000>;
104 clock-names = "baudclk", "apb_pclk";
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart2m0_xfer>;
112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 clock-frequency = <24000000>;
119 clock-names = "baudclk", "apb_pclk";
121 pinctrl-names = "default";
122 pinctrl-0 = <&uart1_xfer>;
127 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
130 reg-shift = <2>;
131 reg-io-width = <4>;
132 clock-frequency = <24000000>;
134 clock-names = "baudclk", "apb_pclk";
136 pinctrl-names = "default";
137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
142 compatible = "rockchip,rv1108-i2c";
145 #address-cells = <1>;
146 #size-cells = <0>;
148 clock-names = "i2c", "pclk";
149 pinctrl-names = "default";
150 pinctrl-0 = <&i2c1_xfer>;
156 compatible = "rockchip,rv1108-i2c";
159 #address-cells = <1>;
160 #size-cells = <0>;
162 clock-names = "i2c", "pclk";
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c2m1_xfer>;
170 compatible = "rockchip,rv1108-i2c";
173 #address-cells = <1>;
174 #size-cells = <0>;
176 clock-names = "i2c", "pclk";
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c3_xfer>;
184 compatible = "rockchip,rv1108-spi";
188 clock-names = "spiclk", "apb_pclk";
190 dma-names = "tx", "rx";
191 #address-cells = <1>;
192 #size-cells = <0>;
197 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
201 clock-names = "pwm", "pclk";
202 pinctrl-names = "default";
203 pinctrl-0 = <&pwm4_pin>;
204 #pwm-cells = <3>;
209 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
213 clock-names = "pwm", "pclk";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pwm5_pin>;
216 #pwm-cells = <3>;
221 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
225 clock-names = "pwm", "pclk";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pwm6_pin>;
228 #pwm-cells = <3>;
233 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
237 clock-names = "pwm", "pclk";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pwm7_pin>;
240 #pwm-cells = <3>;
244 pdma: dma-controller@102a0000 {
248 #dma-cells = <1>;
249 arm,pl330-broken-no-flushp;
250 arm,pl330-periph-burst;
252 clock-names = "apb_pclk";
256 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
258 #address-cells = <1>;
259 #size-cells = <1>;
261 io_domains: io-domains {
262 compatible = "rockchip,rv1108-io-voltage-domain";
267 compatible = "rockchip,rv1108-usb2phy";
270 clock-names = "phyclk";
271 #clock-cells = <0>;
272 clock-output-names = "usbphy";
276 u2phy_otg: otg-port {
278 interrupt-names = "otg-mux";
279 #phy-cells = <0>;
283 u2phy_host: host-port {
285 interrupt-names = "linestate";
286 #phy-cells = <0>;
293 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
297 clock-names = "pclk", "timer";
301 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
308 thermal-zones {
309 soc_thermal: soc-thermal {
310 polling-delay-passive = <20>;
311 polling-delay = <1000>;
312 sustainable-power = <50>;
313 thermal-sensors = <&tsadc 0>;
316 threshold: trip-point0 {
321 target: trip-point1 {
326 soc_crit: soc-crit {
333 cooling-maps {
336 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
344 compatible = "rockchip,rv1108-tsadc";
347 assigned-clocks = <&cru SCLK_TSADC>;
348 assigned-clock-rates = <750000>;
350 clock-names = "tsadc", "apb_pclk";
351 pinctrl-names = "init", "default", "sleep";
352 pinctrl-0 = <&otp_pin>;
353 pinctrl-1 = <&otp_out>;
354 pinctrl-2 = <&otp_pin>;
356 reset-names = "tsadc-apb";
357 rockchip,hw-tshut-temp = <120000>;
358 #thermal-sensor-cells = <1>;
363 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
366 #io-channel-cells = <1>;
368 clock-names = "saradc", "apb_pclk";
373 compatible = "rockchip,rv1108-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c0_xfer>;
387 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
391 clock-names = "pwm", "pclk";
392 pinctrl-names = "default";
393 pinctrl-0 = <&pwm0_pin>;
394 #pwm-cells = <3>;
399 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
403 clock-names = "pwm", "pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&pwm1_pin>;
406 #pwm-cells = <3>;
411 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
415 clock-names = "pwm", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&pwm2_pin>;
418 #pwm-cells = <3>;
423 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
427 clock-names = "pwm", "pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm3_pin>;
430 #pwm-cells = <3>;
435 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
438 pmu_io_domains: io-domains {
439 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
445 compatible = "rockchip,rv1108-usbgrf", "syscon";
449 cru: clock-controller@20200000 {
450 compatible = "rockchip,rv1108-cru";
453 clock-names = "xin24m";
455 #clock-cells = <1>;
456 #reset-cells = <1>;
459 nfc: nand-controller@30100000 {
460 compatible = "rockchip,rv1108-nfc";
464 clock-names = "ahb", "nfc";
465 assigned-clocks = <&cru SCLK_NANDC>;
466 assigned-clock-rates = <150000000>;
471 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
476 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
477 fifo-depth = <0x100>;
478 max-frequency = <150000000>;
483 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
488 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
489 fifo-depth = <0x100>;
490 max-frequency = <150000000>;
495 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
500 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
501 fifo-depth = <0x100>;
502 max-frequency = <100000000>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
509 compatible = "generic-ehci";
514 phy-names = "usb";
519 compatible = "generic-ohci";
524 phy-names = "usb";
529 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
534 clock-names = "otg";
536 g-np-tx-fifo-size = <16>;
537 g-rx-fifo-size = <280>;
538 g-tx-fifo-size = <256 128 128 64 32 16>;
540 phy-names = "usb2-phy";
549 clock-names = "clk_sfc", "hclk_sfc";
550 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
551 pinctrl-names = "default";
555 gmac: ethernet@30200000 {
556 compatible = "rockchip,rv1108-gmac";
560 interrupt-names = "macirq", "eth_wake_irq";
565 clock-names = "stmmaceth",
570 phy-mode = "rmii";
571 pinctrl-names = "default";
572 pinctrl-0 = <&rmii_pins>;
577 gic: interrupt-controller@32010000 {
578 compatible = "arm,gic-400";
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 #address-cells = <0>;
591 compatible = "rockchip,rv1108-pinctrl";
594 #address-cells = <1>;
595 #size-cells = <1>;
599 compatible = "rockchip,gpio-bank";
604 gpio-controller;
605 #gpio-cells = <2>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
612 compatible = "rockchip,gpio-bank";
617 gpio-controller;
618 #gpio-cells = <2>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
625 compatible = "rockchip,gpio-bank";
630 gpio-controller;
631 #gpio-cells = <2>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
638 compatible = "rockchip,gpio-bank";
643 gpio-controller;
644 #gpio-cells = <2>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
650 pcfg_pull_up: pcfg-pull-up {
651 bias-pull-up;
654 pcfg_pull_down: pcfg-pull-down {
655 bias-pull-down;
658 pcfg_pull_none: pcfg-pull-none {
659 bias-disable;
662 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
663 drive-strength = <8>;
666 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
667 drive-strength = <12>;
670 pcfg_pull_none_smt: pcfg-pull-none-smt {
671 bias-disable;
672 input-schmitt-enable;
675 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
676 bias-pull-up;
677 drive-strength = <8>;
680 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
681 drive-strength = <4>;
684 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
685 bias-pull-up;
686 drive-strength = <4>;
689 pcfg_output_high: pcfg-output-high {
690 output-high;
693 pcfg_output_low: pcfg-output-low {
694 output-low;
697 pcfg_input_high: pcfg-input-high {
698 bias-pull-up;
699 input-enable;
703 emmc_bus8: emmc-bus8 {
714 emmc_clk: emmc-clk {
718 emmc_cmd: emmc-cmd {
724 sfc_bus4: sfc-bus4 {
732 sfc_bus2: sfc-bus2 {
738 sfc_cs0: sfc-cs0 {
743 sfc_clk: sfc-clk {
750 rmii_pins: rmii-pins {
765 i2c0_xfer: i2c0-xfer {
772 i2c1_xfer: i2c1-xfer {
779 i2c2m1_xfer: i2c2m1-xfer {
784 i2c2m1_pins: i2c2m1-pins {
791 i2c2m05v_xfer: i2c2m05v-xfer {
796 i2c2m05v_pins: i2c2m05v-pins {
803 i2c3_xfer: i2c3-xfer {
810 pwm0_pin: pwm0-pin {
816 pwm1_pin: pwm1-pin {
822 pwm2_pin: pwm2-pin {
828 pwm3_pin: pwm3-pin {
834 pwm4_pin: pwm4-pin {
840 pwm5_pin: pwm5-pin {
846 pwm6_pin: pwm6-pin {
852 pwm7_pin: pwm7-pin {
858 sdmmc_clk: sdmmc-clk {
862 sdmmc_cmd: sdmmc-cmd {
866 sdmmc_cd: sdmmc-cd {
870 sdmmc_bus1: sdmmc-bus1 {
874 sdmmc_bus4: sdmmc-bus4 {
883 spim0_clk: spim0-clk {
887 spim0_cs0: spim0-cs0 {
891 spim0_tx: spim0-tx {
895 spim0_rx: spim0-rx {
901 spim1_clk: spim1-clk {
905 spim1_cs0: spim1-cs0 {
909 spim1_rx: spim1-rx {
913 spim1_tx: spim1-tx {
919 otp_out: otp-out {
923 otp_pin: otp-pin {
929 uart0_xfer: uart0-xfer {
934 uart0_cts: uart0-cts {
938 uart0_rts: uart0-rts {
942 uart0_rts_pin: uart0-rts-pin {
948 uart1_xfer: uart1-xfer {
953 uart1_cts: uart1-cts {
957 uart1_rts: uart1-rts {
963 uart2m0_xfer: uart2m0-xfer {
970 uart2m1_xfer: uart2m1-xfer {
977 uart2_5v_cts: uart2_5v-cts {
981 uart2_5v_rts: uart2_5v-rts {