Lines Matching full:cru
42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
44 assigned-clocks = <&cru ACLK_GPU>;
46 resets = <&cru SRST_GPU>;
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
78 clocks = <&cru CORE_PERI>;
92 clocks = <&cru CORE_PERI>;
110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
169 clocks = <&cru HCLK_OTG0>;
184 clocks = <&cru HCLK_OTG1>;
199 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
216 resets = <&cru SRST_SDMMC>;
225 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
230 resets = <&cru SRST_SDIO>;
239 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
244 resets = <&cru SRST_EMMC>;
253 clocks = <&cru HCLK_NANDC0>;
285 clocks = <&cru ACLK_DMA1>;
297 clocks = <&cru ACLK_DMA1>;
312 clocks = <&cru PCLK_I2C0>;
326 clocks = <&cru PCLK_I2C1>;
336 clocks = <&cru PCLK_PWM01>;
344 clocks = <&cru PCLK_PWM01>;
351 clocks = <&cru PCLK_WDT>;
360 clocks = <&cru PCLK_PWM23>;
368 clocks = <&cru PCLK_PWM23>;
381 clocks = <&cru PCLK_I2C2>;
396 clocks = <&cru PCLK_I2C3>;
411 clocks = <&cru PCLK_I2C4>;
424 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
435 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
444 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
446 resets = <&cru SRST_SARADC>;
453 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
466 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
485 clocks = <&cru ACLK_DMA2>;