Lines Matching +full:gp +full:- +full:pwm3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points =
35 clock-latency = <40000>;
40 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
46 display-subsystem {
47 compatible = "rockchip,display-subsystem";
52 compatible = "mmio-sram";
54 #address-cells = <1>;
55 #size-cells = <1>;
58 smp-sram@0 {
59 compatible = "rockchip,rk3066-smp-sram";
65 compatible = "rockchip,rk3066-vop";
71 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
72 power-domains = <&power RK3066_PD_VIO>;
76 reset-names = "axi", "ahb", "dclk";
80 #address-cells = <1>;
81 #size-cells = <0>;
85 remote-endpoint = <&hdmi_in_vop0>;
91 compatible = "rockchip,rk3066-vop";
97 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
98 power-domains = <&power RK3066_PD_VIO>;
102 reset-names = "axi", "ahb", "dclk";
106 #address-cells = <1>;
107 #size-cells = <0>;
111 remote-endpoint = <&hdmi_in_vop1>;
117 compatible = "rockchip,rk3066-hdmi";
121 clock-names = "hclk";
122 pinctrl-names = "default";
123 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
124 power-domains = <&power RK3066_PD_VIO>;
129 #address-cells = <1>;
130 #size-cells = <0>;
134 #address-cells = <1>;
135 #size-cells = <0>;
139 remote-endpoint = <&vop0_out_hdmi>;
144 remote-endpoint = <&vop1_out_hdmi>;
155 compatible = "rockchip,rk3066-i2s";
158 pinctrl-names = "default";
159 pinctrl-0 = <&i2s0_bus>;
161 clock-names = "i2s_clk", "i2s_hclk";
163 dma-names = "tx", "rx";
164 rockchip,playback-channels = <8>;
165 rockchip,capture-channels = <2>;
166 #sound-dai-cells = <0>;
171 compatible = "rockchip,rk3066-i2s";
174 pinctrl-names = "default";
175 pinctrl-0 = <&i2s1_bus>;
177 clock-names = "i2s_clk", "i2s_hclk";
179 dma-names = "tx", "rx";
180 rockchip,playback-channels = <2>;
181 rockchip,capture-channels = <2>;
182 #sound-dai-cells = <0>;
187 compatible = "rockchip,rk3066-i2s";
190 pinctrl-names = "default";
191 pinctrl-0 = <&i2s2_bus>;
193 clock-names = "i2s_clk", "i2s_hclk";
195 dma-names = "tx", "rx";
196 rockchip,playback-channels = <2>;
197 rockchip,capture-channels = <2>;
198 #sound-dai-cells = <0>;
202 cru: clock-controller@20000000 {
203 compatible = "rockchip,rk3066a-cru";
206 clock-names = "xin24m";
208 #clock-cells = <1>;
209 #reset-cells = <1>;
210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
214 assigned-clock-rates = <400000000>, <594000000>,
221 compatible = "snps,dw-apb-timer";
225 clock-names = "timer", "pclk";
229 compatible = "rockchip,rk3066a-efuse";
231 #address-cells = <1>;
232 #size-cells = <1>;
234 clock-names = "pclk_efuse";
242 compatible = "snps,dw-apb-timer";
246 clock-names = "timer", "pclk";
250 compatible = "snps,dw-apb-timer";
254 clock-names = "timer", "pclk";
258 compatible = "rockchip,rk3066-tsadc";
261 clock-names = "saradc", "apb_pclk";
263 #io-channel-cells = <1>;
265 reset-names = "saradc-apb";
270 compatible = "rockchip,rk3066a-pinctrl";
272 #address-cells = <1>;
273 #size-cells = <1>;
277 compatible = "rockchip,gpio-bank";
282 gpio-controller;
283 #gpio-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
290 compatible = "rockchip,gpio-bank";
295 gpio-controller;
296 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
303 compatible = "rockchip,gpio-bank";
308 gpio-controller;
309 #gpio-cells = <2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
316 compatible = "rockchip,gpio-bank";
321 gpio-controller;
322 #gpio-cells = <2>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
329 compatible = "rockchip,gpio-bank";
334 gpio-controller;
335 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
342 compatible = "rockchip,gpio-bank";
347 gpio-controller;
348 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
354 pcfg_pull_default: pcfg-pull-default {
355 bias-pull-pin-default;
358 pcfg_pull_none: pcfg-pull-none {
359 bias-disable;
363 emac_xfer: emac-xfer {
374 emac_mdio: emac-mdio {
381 emmc_clk: emmc-clk {
385 emmc_cmd: emmc-cmd {
389 emmc_rst: emmc-rst {
397 * flash/emmc is the boot-device.
402 hdmi_hpd: hdmi-hpd {
406 hdmii2c_xfer: hdmii2c-xfer {
413 i2c0_xfer: i2c0-xfer {
420 i2c1_xfer: i2c1-xfer {
427 i2c2_xfer: i2c2-xfer {
434 i2c3_xfer: i2c3-xfer {
441 i2c4_xfer: i2c4-xfer {
448 pwm0_out: pwm0-out {
454 pwm1_out: pwm1-out {
460 pwm2_out: pwm2-out {
465 pwm3 {
466 pwm3_out: pwm3-out {
472 spi0_clk: spi0-clk {
475 spi0_cs0: spi0-cs0 {
478 spi0_tx: spi0-tx {
481 spi0_rx: spi0-rx {
484 spi0_cs1: spi0-cs1 {
490 spi1_clk: spi1-clk {
493 spi1_cs0: spi1-cs0 {
496 spi1_rx: spi1-rx {
499 spi1_tx: spi1-tx {
502 spi1_cs1: spi1-cs1 {
508 uart0_xfer: uart0-xfer {
513 uart0_cts: uart0-cts {
517 uart0_rts: uart0-rts {
523 uart1_xfer: uart1-xfer {
528 uart1_cts: uart1-cts {
532 uart1_rts: uart1-rts {
538 uart2_xfer: uart2-xfer {
546 uart3_xfer: uart3-xfer {
551 uart3_cts: uart3-cts {
555 uart3_rts: uart3-rts {
561 sd0_clk: sd0-clk {
565 sd0_cmd: sd0-cmd {
569 sd0_cd: sd0-cd {
573 sd0_wp: sd0-wp {
577 sd0_bus1: sd0-bus-width1 {
581 sd0_bus4: sd0-bus-width4 {
590 sd1_clk: sd1-clk {
594 sd1_cmd: sd1-cmd {
598 sd1_cd: sd1-cd {
602 sd1_wp: sd1-wp {
606 sd1_bus1: sd1-bus-width1 {
610 sd1_bus4: sd1-bus-width4 {
619 i2s0_bus: i2s0-bus {
633 i2s1_bus: i2s1-bus {
644 i2s2_bus: i2s2-bus {
657 compatible = "rockchip,rk3066-mali", "arm,mali-400";
668 interrupt-names = "gp",
678 power-domains = <&power RK3066_PD_GPU>;
682 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
685 compatible = "rockchip,rk3066a-usb-phy";
686 #address-cells = <1>;
687 #size-cells = <0>;
690 usbphy0: usb-phy@17c {
693 clock-names = "phyclk";
694 #clock-cells = <0>;
695 #phy-cells = <0>;
698 usbphy1: usb-phy@188 {
701 clock-names = "phyclk";
702 #clock-cells = <0>;
703 #phy-cells = <0>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&i2c0_xfer>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c1_xfer>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c2_xfer>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c3_xfer>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&i2c4_xfer>;
734 clock-frequency = <50000000>;
736 dma-names = "rx-tx";
737 max-frequency = <50000000>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
744 dma-names = "rx-tx";
745 pinctrl-names = "default";
746 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
751 dma-names = "rx-tx";
755 power: power-controller {
756 compatible = "rockchip,rk3066-power-controller";
757 #power-domain-cells = <1>;
758 #address-cells = <1>;
759 #size-cells = <0>;
761 power-domain@RK3066_PD_VIO {
786 #power-domain-cells = <0>;
789 power-domain@RK3066_PD_VIDEO {
796 #power-domain-cells = <0>;
799 power-domain@RK3066_PD_GPU {
803 #power-domain-cells = <0>;
809 pinctrl-names = "default";
810 pinctrl-0 = <&pwm0_out>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&pwm1_out>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&pwm2_out>;
823 &pwm3 {
824 pinctrl-names = "default";
825 pinctrl-0 = <&pwm3_out>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
839 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
841 dma-names = "tx", "rx";
842 pinctrl-names = "default";
843 pinctrl-0 = <&uart0_xfer>;
847 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
849 dma-names = "tx", "rx";
850 pinctrl-names = "default";
851 pinctrl-0 = <&uart1_xfer>;
855 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
857 dma-names = "tx", "rx";
858 pinctrl-names = "default";
859 pinctrl-0 = <&uart2_xfer>;
863 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
865 dma-names = "tx", "rx";
866 pinctrl-names = "default";
867 pinctrl-0 = <&uart3_xfer>;
871 power-domains = <&power RK3066_PD_VIDEO>;
875 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
879 compatible = "rockchip,rk3066-emac";