Lines Matching +full:gp +full:- +full:pwm2
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 interrupt-parent = <&gic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35 enable-method = "rockchip,rk3036-smp";
39 compatible = "arm,cortex-a7";
42 operating-points = <
46 clock-latency = <40000>;
52 compatible = "arm,cortex-a7";
58 arm-pmu {
59 compatible = "arm,cortex-a7-pmu";
62 interrupt-affinity = <&cpu0>, <&cpu1>;
65 display-subsystem {
66 compatible = "rockchip,display-subsystem";
71 compatible = "arm,armv7-timer";
72 arm,cpu-registers-not-fw-configured;
77 clock-frequency = <24000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 clock-output-names = "xin24m";
84 #clock-cells = <0>;
88 compatible = "mmio-sram";
90 #address-cells = <1>;
91 #size-cells = <1>;
94 smp-sram@0 {
95 compatible = "rockchip,rk3066-smp-sram";
101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
107 interrupt-names = "gp",
111 assigned-clocks = <&cru SCLK_GPU>;
112 assigned-clock-rates = <100000000>;
114 clock-names = "bus", "core";
115 power-domains = <&power RK3036_PD_GPU>;
120 vpu: video-codec@10108000 {
121 compatible = "rockchip,rk3036-vpu";
124 interrupt-names = "vdpu";
126 clock-names = "aclk", "hclk";
128 power-domains = <&power RK3036_PD_VPU>;
136 clock-names = "aclk", "iface";
137 power-domains = <&power RK3036_PD_VPU>;
138 #iommu-cells = <0>;
142 compatible = "rockchip,rk3036-vop";
146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
148 reset-names = "axi", "ahb", "dclk";
150 power-domains = <&power RK3036_PD_VIO>;
154 #address-cells = <1>;
155 #size-cells = <0>;
158 remote-endpoint = <&hdmi_in_vop>;
168 clock-names = "aclk", "iface";
169 power-domains = <&power RK3036_PD_VIO>;
170 #iommu-cells = <0>;
175 compatible = "rockchip,rk3036-qos", "syscon";
180 compatible = "rockchip,rk3036-qos", "syscon";
185 compatible = "rockchip,rk3036-qos", "syscon";
189 gic: interrupt-controller@10139000 {
190 compatible = "arm,gic-400";
191 interrupt-controller;
192 #interrupt-cells = <3>;
193 #address-cells = <0>;
203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
208 clock-names = "otg";
210 g-np-tx-fifo-size = <16>;
211 g-rx-fifo-size = <275>;
212 g-tx-fifo-size = <256 128 128 64 64 32>;
217 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
222 clock-names = "otg";
228 compatible = "rockchip,rk3036-emac";
233 clock-names = "hclk", "macref", "macclk";
239 assigned-clocks = <&cru SCLK_MACPLL>;
240 assigned-clock-parents = <&cru PLL_DPLL>;
241 max-speed = <100>;
242 phy-mode = "rmii";
247 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
249 clock-frequency = <37500000>;
250 max-frequency = <37500000>;
252 clock-names = "biu", "ciu";
253 fifo-depth = <0x100>;
256 reset-names = "reset";
261 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
263 max-frequency = <37500000>;
266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 fifo-depth = <0x100>;
270 reset-names = "reset";
275 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
278 bus-width = <8>;
279 cap-mmc-highspeed;
280 clock-frequency = <37500000>;
281 max-frequency = <37500000>;
284 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
285 rockchip,default-sample-phase = <158>;
286 disable-wp;
288 dma-names = "rx-tx";
289 fifo-depth = <0x100>;
290 mmc-ddr-1_8v;
291 non-removable;
292 pinctrl-names = "default";
293 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
295 reset-names = "reset";
300 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
303 clock-names = "i2s_clk", "i2s_hclk";
306 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2s_bus>;
309 #sound-dai-cells = <0>;
313 nfc: nand-controller@10500000 {
314 compatible = "rockchip,rk3036-nfc",
315 "rockchip,rk2928-nfc";
319 clock-names = "ahb", "nfc";
320 assigned-clocks = <&cru SCLK_NANDC>;
321 assigned-clock-rates = <150000000>;
322 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
324 pinctrl-names = "default";
328 cru: clock-controller@20000000 {
329 compatible = "rockchip,rk3036-cru";
332 clock-names = "xin24m";
334 #clock-cells = <1>;
335 #reset-cells = <1>;
336 assigned-clocks = <&cru PLL_GPLL>;
337 assigned-clock-rates = <594000000>;
341 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
344 power: power-controller {
345 compatible = "rockchip,rk3036-power-controller";
346 #power-domain-cells = <1>;
347 #address-cells = <1>;
348 #size-cells = <0>;
350 power-domain@RK3036_PD_VIO {
356 #power-domain-cells = <0>;
359 power-domain@RK3036_PD_VPU {
364 #power-domain-cells = <0>;
367 power-domain@RK3036_PD_GPU {
371 #power-domain-cells = <0>;
375 reboot-mode {
376 compatible = "syscon-reboot-mode";
378 mode-normal = <BOOT_NORMAL>;
379 mode-recovery = <BOOT_RECOVERY>;
380 mode-bootloader = <BOOT_FASTBOOT>;
381 mode-loader = <BOOT_BL_DOWNLOAD>;
385 acodec: acodec-ana@20030000 {
386 compatible = "rk3036-codec";
389 clock-names = "acodec_pclk";
395 compatible = "rockchip,rk3036-inno-hdmi";
399 clock-names = "pclk";
401 pinctrl-names = "default";
402 pinctrl-0 = <&hdmi_ctl>;
406 #address-cells = <1>;
407 #size-cells = <0>;
410 remote-endpoint = <&vop_out_hdmi>;
416 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
420 clock-names = "pclk", "timer";
424 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
426 #pwm-cells = <3>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm0_pin>;
434 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
436 #pwm-cells = <3>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm1_pin>;
443 pwm2: pwm@20050020 { label
444 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
446 #pwm-cells = <3>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm2_pin>;
454 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
456 #pwm-cells = <2>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pwm3_pin>;
464 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clock-names = "i2c";
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2c1_xfer>;
477 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 clock-names = "i2c";
484 pinctrl-names = "default";
485 pinctrl-0 = <&i2c2_xfer>;
490 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
493 reg-shift = <2>;
494 reg-io-width = <4>;
495 clock-frequency = <24000000>;
497 clock-names = "baudclk", "apb_pclk";
498 pinctrl-names = "default";
499 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
504 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
507 reg-shift = <2>;
508 reg-io-width = <4>;
509 clock-frequency = <24000000>;
511 clock-names = "baudclk", "apb_pclk";
512 pinctrl-names = "default";
513 pinctrl-0 = <&uart1_xfer>;
518 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
521 reg-shift = <2>;
522 reg-io-width = <4>;
523 clock-frequency = <24000000>;
525 clock-names = "baudclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart2_xfer>;
532 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 clock-names = "i2c";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c0_xfer>;
545 compatible = "rockchip,rockchip-spi";
549 clock-names = "apb-pclk","spi_pclk";
551 dma-names = "tx", "rx";
552 pinctrl-names = "default";
553 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
554 #address-cells = <1>;
555 #size-cells = <0>;
559 pdma: dma-controller@20078000 {
564 #dma-cells = <1>;
565 arm,pl330-broken-no-flushp;
566 arm,pl330-periph-burst;
568 clock-names = "apb_pclk";
572 compatible = "rockchip,rk3036-pinctrl";
574 #address-cells = <1>;
575 #size-cells = <1>;
579 compatible = "rockchip,gpio-bank";
584 gpio-controller;
585 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
592 compatible = "rockchip,gpio-bank";
597 gpio-controller;
598 #gpio-cells = <2>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
605 compatible = "rockchip,gpio-bank";
610 gpio-controller;
611 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
617 pcfg_pull_default: pcfg-pull-default {
618 bias-pull-pin-default;
621 pcfg_pull_none: pcfg-pull-none {
622 bias-disable;
626 pwm0_pin: pwm0-pin {
632 pwm1_pin: pwm1-pin {
637 pwm2 {
638 pwm2_pin: pwm2-pin {
644 pwm3_pin: pwm3-pin {
650 sdmmc_clk: sdmmc-clk {
654 sdmmc_cmd: sdmmc-cmd {
658 sdmmc_cd: sdmmc-cd {
662 sdmmc_bus1: sdmmc-bus1 {
666 sdmmc_bus4: sdmmc-bus4 {
675 sdio_bus1: sdio-bus1 {
679 sdio_bus4: sdio-bus4 {
686 sdio_cmd: sdio-cmd {
690 sdio_clk: sdio-clk {
700 emmc_clk: emmc-clk {
704 emmc_cmd: emmc-cmd {
708 emmc_bus8: emmc-bus8 {
721 flash_ale: flash-ale {
725 flash_bus8: flash-bus8 {
736 flash_cle: flash-cle {
740 flash_csn0: flash-csn0 {
744 flash_rdn: flash-rdn {
748 flash_rdy: flash-rdy {
752 flash_wrn: flash-wrn {
758 emac_xfer: emac-xfer {
769 emac_mdio: emac-mdio {
776 i2c0_xfer: i2c0-xfer {
783 i2c1_xfer: i2c1-xfer {
790 i2c2_xfer: i2c2-xfer {
797 i2s_bus: i2s-bus {
808 hdmi_ctl: hdmi-ctl {
817 uart0_xfer: uart0-xfer {
822 uart0_cts: uart0-cts {
826 uart0_rts: uart0-rts {
832 uart1_xfer: uart1-xfer {
840 uart2_xfer: uart2-xfer {
847 spi-pins {
848 spi_txd:spi-txd {
852 spi_rxd:spi-rxd {
856 spi_clk:spi-clk {
860 spi_cs0:spi-cs0 {
865 spi_cs1:spi-cs1 {