Lines Matching +full:0 +full:x20064000
34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
133 reg = <0x10108800 0x100>;
138 #iommu-cells = <0>;
143 reg = <0x10118000 0x19c>;
155 #size-cells = <0>;
156 vop_out_hdmi: endpoint@0 {
157 reg = <0>;
165 reg = <0x10118300 0x100>;
170 #iommu-cells = <0>;
176 reg = <0x1012d000 0x20>;
181 reg = <0x1012e000 0x20>;
186 reg = <0x1012f000 0x20>;
193 #address-cells = <0>;
195 reg = <0x10139000 0x1000>,
196 <0x1013a000 0x2000>,
197 <0x1013c000 0x2000>,
198 <0x1013e000 0x2000>;
205 reg = <0x10180000 0x40000>;
219 reg = <0x101c0000 0x40000>;
229 reg = <0x10200000 0x4000>;
248 reg = <0x10214000 0x4000>;
253 fifo-depth = <0x100>;
262 reg = <0x10218000 0x4000>;
267 fifo-depth = <0x100>;
276 reg = <0x1021c000 0x4000>;
289 fifo-depth = <0x100>;
293 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
301 reg = <0x10220000 0x4000>;
305 dmas = <&pdma 0>, <&pdma 1>;
308 pinctrl-0 = <&i2s_bus>;
309 #sound-dai-cells = <0>;
316 reg = <0x10500000 0x4000>;
322 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
330 reg = <0x20000000 0x1000>;
342 reg = <0x20008000 0x1000>;
348 #size-cells = <0>;
356 #power-domain-cells = <0>;
364 #power-domain-cells = <0>;
371 #power-domain-cells = <0>;
377 offset = <0x1d8>;
387 reg = <0x20030000 0x4000>;
396 reg = <0x20034000 0x4000>;
402 pinctrl-0 = <&hdmi_ctl>;
407 #size-cells = <0>;
408 hdmi_in_vop: endpoint@0 {
409 reg = <0>;
417 reg = <0x20044000 0x20>;
425 reg = <0x20050000 0x10>;
429 pinctrl-0 = <&pwm0_pin>;
435 reg = <0x20050010 0x10>;
439 pinctrl-0 = <&pwm1_pin>;
445 reg = <0x20050020 0x10>;
449 pinctrl-0 = <&pwm2_pin>;
455 reg = <0x20050030 0x10>;
459 pinctrl-0 = <&pwm3_pin>;
465 reg = <0x20056000 0x1000>;
468 #size-cells = <0>;
472 pinctrl-0 = <&i2c1_xfer>;
478 reg = <0x2005a000 0x1000>;
481 #size-cells = <0>;
485 pinctrl-0 = <&i2c2_xfer>;
491 reg = <0x20060000 0x100>;
499 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
505 reg = <0x20064000 0x100>;
513 pinctrl-0 = <&uart1_xfer>;
519 reg = <0x20068000 0x100>;
527 pinctrl-0 = <&uart2_xfer>;
533 reg = <0x20072000 0x1000>;
536 #size-cells = <0>;
540 pinctrl-0 = <&i2c0_xfer>;
546 reg = <0x20074000 0x1000>;
553 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
555 #size-cells = <0>;
561 reg = <0x20078000 0x4000>;
562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
580 reg = <0x2007c000 0x100>;
593 reg = <0x20080000 0x100>;
606 reg = <0x20084000 0x100>;
627 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
633 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
639 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
645 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
676 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
680 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
681 <0 RK_PB4 1 &pcfg_pull_default>,
682 <0 RK_PB5 1 &pcfg_pull_default>,
683 <0 RK_PB6 1 &pcfg_pull_default>;
687 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
691 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
777 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
778 <0 RK_PA1 1 &pcfg_pull_none>;
784 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
785 <0 RK_PA3 1 &pcfg_pull_none>;
818 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
819 <0 RK_PC1 1 &pcfg_pull_none>;
823 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
827 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;