Lines Matching +full:intc +full:- +full:irqpin
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a9";
28 clock-frequency = <1000000000>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
37 power-domains = <&sysc R8A7779_PD_ARM1>;
41 compatible = "arm,cortex-a9";
43 clock-frequency = <1000000000>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
49 compatible = "arm,cortex-a9";
51 clock-frequency = <1000000000>;
53 power-domains = <&sysc R8A7779_PD_ARM3>;
63 gic: interrupt-controller@f0001000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
72 compatible = "arm,cortex-a9-global-timer";
80 compatible = "arm,cortex-a9-twd-timer";
88 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
91 #gpio-cells = <2>;
92 gpio-controller;
93 gpio-ranges = <&pfc 0 0 32>;
94 #interrupt-cells = <2>;
95 interrupt-controller;
99 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
102 #gpio-cells = <2>;
103 gpio-controller;
104 gpio-ranges = <&pfc 0 32 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
110 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
113 #gpio-cells = <2>;
114 gpio-controller;
115 gpio-ranges = <&pfc 0 64 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
121 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
132 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
135 #gpio-cells = <2>;
136 gpio-controller;
137 gpio-ranges = <&pfc 0 128 32>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
143 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
146 #gpio-cells = <2>;
147 gpio-controller;
148 gpio-ranges = <&pfc 0 160 32>;
149 #interrupt-cells = <2>;
150 interrupt-controller;
154 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 192 9>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
164 irqpin0: interrupt-controller@fe78001c {
165 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166 #interrupt-cells = <2>;
168 interrupt-controller;
179 sense-bitfield-width = <2>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
189 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
200 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
201 i2c-scl-internal-delay-ns = <5>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
212 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
213 i2c-scl-internal-delay-ns = <5>;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
224 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
225 i2c-scl-internal-delay-ns = <5>;
230 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
236 clock-names = "fck", "brg_int", "scif_clk";
237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
242 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
248 clock-names = "fck", "brg_int", "scif_clk";
249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
254 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
260 clock-names = "fck", "brg_int", "scif_clk";
261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
266 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
272 clock-names = "fck", "brg_int", "scif_clk";
273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
278 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
284 clock-names = "fck", "brg_int", "scif_clk";
285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
290 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
296 clock-names = "fck", "brg_int", "scif_clk";
297 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
302 compatible = "renesas,hscif-r8a7779",
303 "renesas,rcar-gen1-hscif", "renesas,hscif";
309 clock-names = "fck", "brg_int", "scif_clk";
310 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
315 compatible = "renesas,hscif-r8a7779",
316 "renesas,rcar-gen1-hscif", "renesas,hscif";
322 clock-names = "fck", "brg_int", "scif_clk";
323 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
328 compatible = "renesas,pfc-r8a7779";
333 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
338 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
344 clock-names = "fck";
345 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
353 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
359 clock-names = "fck";
360 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
368 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
374 clock-names = "fck";
375 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
383 compatible = "renesas,sata-r8a7779";
387 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
392 compatible = "renesas,sdhi-r8a7779",
393 "renesas,rcar-gen1-sdhi";
397 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
402 compatible = "renesas,sdhi-r8a7779",
403 "renesas,rcar-gen1-sdhi";
407 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
412 compatible = "renesas,sdhi-r8a7779",
413 "renesas,rcar-gen1-sdhi";
417 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
422 compatible = "renesas,sdhi-r8a7779",
423 "renesas,rcar-gen1-sdhi";
427 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
432 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
435 #address-cells = <1>;
436 #size-cells = <0>;
438 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
443 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
446 #address-cells = <1>;
447 #size-cells = <0>;
449 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
454 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
457 #address-cells = <1>;
458 #size-cells = <0>;
460 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
465 compatible = "renesas,du-r8a7779";
469 clock-names = "du.0";
470 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
474 #address-cells = <1>;
475 #size-cells = <0>;
491 #address-cells = <1>;
492 #size-cells = <1>;
497 compatible = "fixed-clock";
498 #clock-cells = <0>;
500 clock-frequency = <0>;
505 compatible = "fixed-clock";
506 #clock-cells = <0>;
508 clock-frequency = <0>;
513 compatible = "renesas,r8a7779-cpg-clocks";
516 #clock-cells = <1>;
517 clock-output-names = "plla", "z", "zs", "s",
519 #power-domain-cells = <0>;
524 compatible = "fixed-factor-clock";
526 #clock-cells = <0>;
527 clock-div = <2>;
528 clock-mult = <1>;
531 compatible = "fixed-factor-clock";
533 #clock-cells = <0>;
534 clock-div = <8>;
535 clock-mult = <1>;
538 compatible = "fixed-factor-clock";
540 #clock-cells = <0>;
541 clock-div = <16>;
542 clock-mult = <1>;
545 compatible = "fixed-factor-clock";
547 #clock-cells = <0>;
548 clock-div = <24>;
549 clock-mult = <1>;
554 compatible = "renesas,r8a7779-mstp-clocks",
555 "renesas,cpg-mstp-clocks";
573 #clock-cells = <1>;
574 clock-indices = <
584 clock-output-names =
591 compatible = "renesas,r8a7779-mstp-clocks",
592 "renesas,cpg-mstp-clocks";
604 #clock-cells = <1>;
605 clock-indices = <
612 clock-output-names =
620 compatible = "renesas,r8a7779-mstp-clocks",
621 "renesas,cpg-mstp-clocks";
625 #clock-cells = <1>;
626 clock-indices = <
631 clock-output-names =
642 rst: reset-controller@ffcc0000 {
643 compatible = "renesas,r8a7779-reset-wdt";
647 sysc: system-controller@ffd85000 {
648 compatible = "renesas,r8a7779-sysc";
650 #power-domain-cells = <1>;