Lines Matching +full:0 +full:xffe40000

26 		#size-cells = <0>;
28 		cpu@0 {
31 			reg = <0>;
47 		ranges = <0 0 0x1c000000>;
53 		reg = <0xfde00000 0x400>;
59 		#size-cells = <0>;
67 		reg = <0xfe438000 0x1000>,
68 		      <0xfe430000 0x100>;
77 		reg =	<0xfe78001c 4>,
78 			<0xfe780010 4>,
79 			<0xfe780024 4>,
80 			<0xfe780044 4>,
81 			<0xfe780064 4>,
82 			<0xfe780000 4>;
92 		reg = <0xffc40000 0x2c>;
96 		gpio-ranges = <&pfc 0 0 32>;
103 		reg = <0xffc41000 0x2c>;
107 		gpio-ranges = <&pfc 0 32 32>;
114 		reg = <0xffc42000 0x2c>;
118 		gpio-ranges = <&pfc 0 64 32>;
125 		reg = <0xffc43000 0x2c>;
129 		gpio-ranges = <&pfc 0 96 32>;
136 		reg = <0xffc44000 0x2c>;
140 		gpio-ranges = <&pfc 0 128 27>;
147 		reg = <0xfffc0000 0x118>;
152 		#size-cells = <0>;
154 		reg = <0xffc70000 0x1000>;
163 		#size-cells = <0>;
165 		reg = <0xffc71000 0x1000>;
175 		#size-cells = <0>;
177 		reg = <0xffc72000 0x1000>;
187 		#size-cells = <0>;
189 		reg = <0xffc73000 0x1000>;
199 		reg = <0xffd80000 0x30>;
214 		reg = <0xffd81000 0x30>;
229 		reg = <0xffd82000 0x30>;
246 		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
250 		reg =	<0xffd90000 0x1000>,	/* SRU */
251 			<0xffd91000 0x240>,	/* SSI */
252 			<0xfffe0000 0x24>;	/* ADG */
274 			"ssi.3", "ssi.2", "ssi.1", "ssi.0",
276 			"src.3", "src.2", "src.1", "src.0",
292 			ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
293 			ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
294 			ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
295 			ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
296 			ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
297 			ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
298 			ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
305 		reg = <0xffe40000 0x100>;
317 		reg = <0xffe41000 0x100>;
329 		reg = <0xffe42000 0x100>;
341 		reg = <0xffe43000 0x100>;
353 		reg = <0xffe44000 0x100>;
365 		reg = <0xffe45000 0x100>;
377 		reg = <0xffe48000 96>;
389 		reg = <0xffe49000 96>;
400 		reg = <0xffe4e000 0x100>;
410 		reg = <0xffe4c000 0x100>;
420 		reg = <0xffe4d000 0x100>;
430 		reg = <0xffe4f000 0x100>;
439 		reg = <0xfffc7000 0x18>;
444 		#size-cells = <0>;
450 		reg = <0xfffc8000 0x18>;
455 		#size-cells = <0>;
461 		reg = <0xfffc6000 0x18>;
466 		#size-cells = <0>;
478 			#clock-cells = <0>;
479 			clock-frequency = <0>;
485 			#clock-cells = <0>;
487 			clock-frequency = <0>;
493 			reg = <0xffc80000 0x80>;
498 			#power-domain-cells = <0>;
504 			#clock-cells = <0>;
505 			clock-frequency = <0>;
509 			#clock-cells = <0>;
510 			clock-frequency = <0>;
514 			#clock-cells = <0>;
515 			clock-frequency = <0>;
522 			#clock-cells = <0>;
529 			#clock-cells = <0>;
536 			#clock-cells = <0>;
543 			#clock-cells = <0>;
550 			#clock-cells = <0>;
558 			reg = <0xffc80030 4>;
603 			reg = <0xffc80034 4>, <0xffc80044 4>;
618 			reg = <0xffc8003c 4>;
642 			reg = <0xffc80054 4>;
669 		reg = <0xffcc0000 0x40>;