Lines Matching +full:0 +full:xfcfec000
32 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
55 #clock-cells = <0>;
58 clock-frequency = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
79 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 #clock-cells = <0>;
86 clock-frequency = <0>;
90 #clock-cells = <0>;
93 clock-frequency = <0>;
106 reg = <0x3ffff000 0x1000>;
116 reg = <0xe8007000 64>;
129 reg = <0xe8007800 64>;
142 reg = <0xe8008000 64>;
155 reg = <0xe8008800 64>;
168 reg = <0xe8009000 64>;
181 reg = <0xe8009800 64>;
194 reg = <0xe800a000 64>;
207 reg = <0xe800a800 64>;
220 reg = <0xe800c800 0x24>;
229 #size-cells = <0>;
235 reg = <0xe800d000 0x24>;
244 #size-cells = <0>;
250 reg = <0xe800d800 0x24>;
259 #size-cells = <0>;
265 reg = <0xe800e000 0x24>;
274 #size-cells = <0>;
280 reg = <0xe800e800 0x24>;
289 #size-cells = <0>;
295 reg = <0xe8010000 0x1a0>;
305 reg = <0xe8207000 0x1a0>;
315 reg = <0xe804c800 0x80>;
328 reg = <0xe804e000 0x100>;
344 reg = <0xe804e800 0x100>;
361 #address-cells = <0>;
363 reg = <0xe8201000 0x1000>,
364 <0xe8202000 0x1000>;
369 reg = <0xe8203000 0x800>,
370 <0xe8204800 0x200>;
376 #size-cells = <0>;
381 reg = <0xe8210000 0x3000>;
391 reg = <0xfcfe0000 0x6>;
401 reg = <0xfcfe0000 0x18>;
404 #power-domain-cells = <0>;
411 reg = <0xfcfe0420 4>;
420 reg = <0xfcfe0424 4>;
433 reg = <0xfcfe0428 4>;
442 reg = <0xfcfe042c 4>;
451 reg = <0xfcfe0430 4>;
460 reg = <0xfcfe0434 4>;
469 reg = <0xfcfe0438 4>;
481 reg = <0xfcfe043c 4>;
493 reg = <0xfcfe0444 4>;
505 reg = <0xfcfe3000 0x4230>;
507 port0: gpio-0 {
510 gpio-ranges = <&pinctrl 0 0 6>;
516 gpio-ranges = <&pinctrl 0 16 16>;
522 gpio-ranges = <&pinctrl 0 32 16>;
528 gpio-ranges = <&pinctrl 0 48 16>;
534 gpio-ranges = <&pinctrl 0 64 16>;
540 gpio-ranges = <&pinctrl 0 80 11>;
546 gpio-ranges = <&pinctrl 0 96 16>;
552 gpio-ranges = <&pinctrl 0 112 16>;
558 gpio-ranges = <&pinctrl 0 128 16>;
564 gpio-ranges = <&pinctrl 0 144 8>;
570 gpio-ranges = <&pinctrl 0 160 16>;
576 gpio-ranges = <&pinctrl 0 176 16>;
582 reg = <0xfcfec000 0x30>;
591 reg = <0xfcfec400 0x30>;
600 #size-cells = <0>;
602 reg = <0xfcfee000 0x44>;
621 #size-cells = <0>;
623 reg = <0xfcfee400 0x44>;
642 #size-cells = <0>;
644 reg = <0xfcfee800 0x44>;
663 #size-cells = <0>;
665 reg = <0xfcfeec00 0x44>;
686 #address-cells = <0>;
688 reg = <0xfcfef800 0x6>;
690 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
691 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
692 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
693 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
694 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
695 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
696 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
697 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-map-mask = <7 0>;
703 reg = <0xfcff0000 0x400>;
714 reg = <0xfcff1000 0x2e>;
728 #clock-cells = <0>;
731 clock-frequency = <0>;