Lines Matching +full:0 +full:xfd4a0000
20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
107 reg = <0x0 0x0>;
112 interrupts = <GIC_PPI 7 0xf04>;
121 reg = <0x08000000 0x5100000>;
126 reg = <0x0d100000 0x100000>;
131 reg = <0x0d200000 0xa00000>;
136 reg = <0x0dc00000 0x1900000>;
141 reg = <0x0f500000 0x500000>;
146 reg = <0xfa00000 0x200000>;
151 reg = <0x0fc00000 0x160000>;
156 reg = <0x0fd60000 0x20000>;
162 reg = <0x0fd80000 0x180000>;
187 qcom,local-pid = <0>;
212 qcom,local-pid = <0>;
237 qcom,local-pid = <0>;
258 #size-cells = <0>;
264 apps_smsm: apps@0 {
265 reg = <0>;
300 qcom,ipc = <&apcs 8 0>;
325 reg = <0xf9000000 0x1000>,
326 <0xf9002000 0x1000>;
331 reg = <0xf9011000 0x1000>;
339 reg = <0xf9020000 0x1000>;
343 frame-number = <0>;
346 reg = <0xf9021000 0x1000>,
347 <0xf9022000 0x1000>;
353 reg = <0xf9023000 0x1000>;
360 reg = <0xf9024000 0x1000>;
367 reg = <0xf9025000 0x1000>;
374 reg = <0xf9026000 0x1000>;
381 reg = <0xf9027000 0x1000>;
388 reg = <0xf9028000 0x1000>;
395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
415 reg = <0xf9012000 0x1000>;
421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
470 #size-cells = <0>;
477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
489 #size-cells = <0>;
496 reg = <0xf991d000 0x1000>;
505 reg = <0xf991e000 0x1000>;
510 pinctrl-0 = <&blsp1_uart2_default>;
517 reg = <0xf9923000 0x1000>;
518 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-0 = <&blsp1_i2c1_default>;
525 #size-cells = <0>;
531 reg = <0xf9924000 0x1000>;
536 pinctrl-0 = <&blsp1_i2c2_default>;
539 #size-cells = <0>;
545 reg = <0xf9925000 0x1000>;
546 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-0 = <&blsp1_i2c3_default>;
553 #size-cells = <0>;
559 reg = <0xf9928000 0x1000>;
564 pinctrl-0 = <&blsp1_i2c6_default>;
567 #size-cells = <0>;
572 reg = <0xf9944000 0x19000>;
577 qcom,ee = <0>;
582 reg = <0xf995d000 0x1000>;
587 pinctrl-0 = <&blsp2_uart1_default>;
594 reg = <0xf995e000 0x1000>;
603 reg = <0xf9960000 0x1000>;
608 pinctrl-0 = <&blsp2_uart4_default>;
615 reg = <0xf9964000 0x1000>;
620 pinctrl-0 = <&blsp2_i2c2_default>;
623 #size-cells = <0>;
629 reg = <0xf9967000 0x1000>;
636 pinctrl-0 = <&blsp2_i2c5_default>;
639 #size-cells = <0>;
645 reg = <0xf9968000 0x1000>;
646 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
650 pinctrl-0 = <&blsp2_i2c6_default>;
653 #size-cells = <0>;
658 reg = <0xf9a55000 0x200>,
659 <0xf9a55200 0x200>;
670 ahb-burst-config = <0>;
679 #phy-cells = <0>;
682 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
690 #phy-cells = <0>;
702 reg = <0xf9bff000 0x200>;
709 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
715 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
721 qcom,smem-states = <&wcnss_smp2p_out 0>;
767 reg = <0xfc190000 0x10000>;
772 reg = <0xfc307000 0x1000>;
796 reg = <0xfc318000 0x1000>;
812 reg = <0xfc31a000 0x1000>;
819 #size-cells = <0>;
823 * 0 - not-connected
850 reg = <0xfc31b000 0x1000>;
857 #size-cells = <0>;
861 * 0 - connected trought funnel to Audio, Modem and
884 reg = <0xfc31c000 0x1000>;
891 #size-cells = <0>;
893 port@0 {
894 reg = <0>;
918 reg = <0xfc322000 0x1000>;
934 reg = <0xfc33c000 0x1000>;
952 reg = <0xfc33d000 0x1000>;
970 reg = <0xfc33e000 0x1000>;
988 reg = <0xfc33f000 0x1000>;
1007 reg = <0xfc345000 0x1000>;
1014 #size-cells = <0>;
1016 port@0 {
1017 reg = <0>;
1056 reg = <0xfc400000 0x4000>;
1061 reg = <0xfc428000 0x4000>;
1065 reg = <0xfc380000 0x6a000>;
1074 reg = <0xfc460000 0x4000>;
1083 reg = <0xfc468000 0x4000>;
1092 reg = <0xfc470000 0x4000>;
1101 reg = <0xfc478000 0x4000>;
1110 reg = <0xfc480000 0x4000>;
1120 reg = <0xfc4a9000 0x1000>, /* TM */
1121 <0xfc4a8000 0x1000>; /* SROT */
1132 reg = <0xfc4ab000 0x4>;
1137 reg = <0xfc4bc000 0x1000>;
1141 reg = <0xd0 0x18>;
1144 reg = <0x440 0x10>;
1151 reg = <0xfc4cf000 0x1000>,
1152 <0xfc4cb000 0x1000>,
1153 <0xfc4ca000 0x1000>;
1156 qcom,ee = <0>;
1157 qcom,channel = <0>;
1159 #size-cells = <0>;
1166 reg = <0xfc834000 0x7000>;
1169 qcom,ee = <0>;
1178 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1182 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1197 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
1199 qcom,smem-states = <&modem_smp2p_out 0>;
1230 qcom,smd-edge = <0>;
1238 reg = <0xfd484000 0x2000>;
1243 reg = <0xfd4a0000 0x10000>;
1248 reg = <0xfd510000 0x4000>;
1250 gpio-ranges = <&tlmm 0 0 146>;
1491 reg = <0xfd8c0000 0x6000>;
1496 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1519 reg = <0xfd900100 0x22000>;
1523 interrupts = <0>;
1536 #size-cells = <0>;
1538 port@0 {
1539 reg = <0>;
1549 reg = <0xfd922800 0x1f8>;
1556 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1579 #size-cells = <0>;
1583 #size-cells = <0>;
1585 port@0 {
1586 reg = <0>;
1602 reg = <0xfd922a00 0xd4>,
1603 <0xfd922b00 0x280>,
1604 <0xfd922d80 0x30>;
1610 #phy-cells = <0>;
1621 reg = <0xfdb00000 0x10000>;
1640 // iommus = <&gpu_iommu 0>;
1663 reg = <0xfdd00000 0x2000>,
1664 <0xfec00000 0x180000>;
1666 ranges = <0 0xfec00000 0x180000>;
1674 gmu_sram: gmu-sram@0 {
1675 reg = <0x0 0x100000>;
1681 reg = <0xfe200000 0x100>;
1684 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1695 qcom,smem-states = <&adsp_smp2p_out 0>;
1707 #size-cells = <0>;
1713 reg = <0xfe805000 0x1000>;
1717 offset = <0x65c>;
1724 syscon = <&tcsr_mutex_block 0 0x80>;
1903 interrupts = <GIC_PPI 2 0xf08>,
1904 <GIC_PPI 3 0xf08>,
1905 <GIC_PPI 4 0xf08>,
1906 <GIC_PPI 1 0xf08>;
1924 pinctrl-0 = <&boost_bypass_n_pin>;