Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&intc>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32768>;
42 compatible = "qcom,scm-msm8226", "qcom,scm";
44 clock-names = "core", "bus", "iface";
48 reserved-memory {
49 #address-cells = <1>;
50 #size-cells = <1>;
55 no-map;
60 no-map;
70 qcom,smd-edge = <15>;
72 rpm_requests: rpm-requests {
73 compatible = "qcom,rpm-msm8226";
74 qcom,smd-channels = "rpm_requests";
76 rpmpd: power-controller {
77 compatible = "qcom,msm8226-rpmpd";
78 #power-domain-cells = <1>;
79 operating-points-v2 = <&rpmpd_opp_table>;
81 rpmpd_opp_table: opp-table {
82 compatible = "operating-points-v2";
85 opp-level = <1>;
88 opp-level = <2>;
91 opp-level = <3>;
94 opp-level = <4>;
97 opp-level = <5>;
100 opp-level = <6>;
111 memory-region = <&smem_region>;
112 qcom,rpm-msg-ram = <&rpm_msg_ram>;
117 smp2p-adsp {
121 interrupt-parent = <&intc>;
126 qcom,local-pid = <0>;
127 qcom,remote-pid = <2>;
129 adsp_smp2p_out: master-kernel {
130 qcom,entry-name = "master-kernel";
131 #qcom,smem-state-cells = <1>;
134 adsp_smp2p_in: slave-kernel {
135 qcom,entry-name = "slave-kernel";
137 interrupt-controller;
138 #interrupt-cells = <2>;
143 compatible = "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
148 intc: interrupt-controller@f9000000 {
149 compatible = "qcom,msm-qgic2";
152 interrupt-controller;
153 #interrupt-cells = <3>;
162 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
164 reg-names = "hc", "core";
167 interrupt-names = "hc_irq", "pwr_irq";
171 clock-names = "iface", "core", "xo";
172 pinctrl-names = "default";
173 pinctrl-0 = <&sdhc1_default_state>;
178 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
180 reg-names = "hc", "core";
183 interrupt-names = "hc_irq", "pwr_irq";
187 clock-names = "iface", "core", "xo";
188 pinctrl-names = "default";
189 pinctrl-0 = <&sdhc2_default_state>;
194 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
196 reg-names = "hc", "core";
199 interrupt-names = "hc_irq", "pwr_irq";
203 clock-names = "iface", "core", "xo";
204 pinctrl-names = "default";
205 pinctrl-0 = <&sdhc3_default_state>;
210 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
214 clock-names = "core", "iface";
219 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
223 clock-names = "core", "iface";
228 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
232 clock-names = "core", "iface";
238 compatible = "qcom,i2c-qup-v2.1.1";
242 clock-names = "core", "iface";
243 pinctrl-names = "default";
244 pinctrl-0 = <&blsp1_i2c1_pins>;
245 #address-cells = <1>;
246 #size-cells = <0>;
251 compatible = "qcom,i2c-qup-v2.1.1";
255 clock-names = "core", "iface";
256 pinctrl-names = "default";
257 pinctrl-0 = <&blsp1_i2c2_pins>;
258 #address-cells = <1>;
259 #size-cells = <0>;
264 compatible = "qcom,i2c-qup-v2.1.1";
268 clock-names = "core", "iface";
269 pinctrl-names = "default";
270 pinctrl-0 = <&blsp1_i2c3_pins>;
271 #address-cells = <1>;
272 #size-cells = <0>;
277 compatible = "qcom,i2c-qup-v2.1.1";
281 clock-names = "core", "iface";
282 pinctrl-names = "default";
283 pinctrl-0 = <&blsp1_i2c4_pins>;
284 #address-cells = <1>;
285 #size-cells = <0>;
290 compatible = "qcom,i2c-qup-v2.1.1";
294 clock-names = "core", "iface";
295 pinctrl-names = "default";
296 pinctrl-0 = <&blsp1_i2c5_pins>;
297 #address-cells = <1>;
298 #size-cells = <0>;
302 compatible = "qcom,ci-hdrc";
308 clock-names = "iface", "core";
309 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
310 assigned-clock-rates = <75000000>;
312 reset-names = "core";
315 hnp-disable;
316 srp-disable;
317 adp-disable;
318 ahb-burst-config = <0>;
319 phy-names = "usb-phy";
322 #reset-cells = <1>;
326 compatible = "qcom,usb-hs-phy-msm8226",
327 "qcom,usb-hs-phy";
328 #phy-cells = <0>;
330 clock-names = "ref", "sleep";
332 reset-names = "phy", "por";
333 qcom,init-seq = /bits/ 8 <0x0 0x44
339 gcc: clock-controller@fc400000 {
340 compatible = "qcom,gcc-msm8226";
342 #clock-cells = <1>;
343 #reset-cells = <1>;
344 #power-domain-cells = <1>;
348 compatible = "qcom,msm8226-pinctrl";
350 gpio-controller;
351 #gpio-cells = <2>;
352 gpio-ranges = <&tlmm 0 0 117>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
357 blsp1_i2c1_pins: blsp1-i2c1 {
360 drive-strength = <2>;
361 bias-disable;
364 blsp1_i2c2_pins: blsp1-i2c2 {
367 drive-strength = <2>;
368 bias-disable;
371 blsp1_i2c3_pins: blsp1-i2c3 {
374 drive-strength = <2>;
375 bias-disable;
378 blsp1_i2c4_pins: blsp1-i2c4 {
381 drive-strength = <2>;
382 bias-disable;
385 blsp1_i2c5_pins: blsp1-i2c5 {
388 drive-strength = <2>;
389 bias-disable;
392 sdhc1_default_state: sdhc1-default-state {
395 drive-strength = <10>;
396 bias-disable;
399 cmd-data {
401 drive-strength = <10>;
402 bias-pull-up;
406 sdhc2_default_state: sdhc2-default-state {
409 drive-strength = <10>;
410 bias-disable;
413 cmd-data {
415 drive-strength = <10>;
416 bias-pull-up;
420 sdhc3_default_state: sdhc3-default-state {
424 drive-strength = <8>;
425 bias-disable;
431 drive-strength = <8>;
432 bias-pull-up;
438 drive-strength = <8>;
439 bias-pull-up;
450 compatible = "qcom,spmi-pmic-arb";
451 reg-names = "core", "intr", "cnfg";
455 interrupt-names = "periph_irq";
459 #address-cells = <2>;
460 #size-cells = <0>;
461 interrupt-controller;
462 #interrupt-cells = <4>;
469 clock-names = "core";
473 compatible = "arm,armv7-timer-mem";
475 #address-cells = <1>;
476 #size-cells = <1>;
480 frame-number = <0>;
488 frame-number = <1>;
495 frame-number = <2>;
502 frame-number = <3>;
509 frame-number = <4>;
516 frame-number = <5>;
523 frame-number = <6>;
531 compatible = "qcom,rpm-msg-ram";
536 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
538 #hwlock-cells = <1>;
542 compatible = "qcom,msm8226-adsp-pil";
545 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
550 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
552 power-domains = <&rpmpd MSM8226_VDDCX>;
553 power-domain-names = "cx";
556 clock-names = "xo";
558 memory-region = <&adsp_region>;
560 qcom,smem-states = <&adsp_smp2p_out 0>;
561 qcom,smem-state-names = "stop";
565 smd-edge {
569 qcom,smd-edge = <1>;
577 compatible = "arm,armv7-timer";