Lines Matching +full:usb +full:- +full:hs +full:- +full:ipq4019 +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
27 no-map;
32 no-map;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
102 L2: l2-cache {
104 cache-level = <2>;
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-48000000 {
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
117 opp-200000000 {
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
121 opp-500000000 {
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
125 opp-716000000 {
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
137 compatible = "arm,cortex-a7-pmu";
144 compatible = "fixed-clock";
145 clock-frequency = <32000>;
146 clock-output-names = "gcc_sleep_clk_src";
147 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
153 #clock-cells = <0>;
159 compatible = "qcom,scm-ipq4019", "qcom,scm";
164 compatible = "arm,armv7-timer";
169 clock-frequency = <48000000>;
170 always-on;
174 #address-cells = <1>;
175 #size-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
187 gcc: clock-controller@1800000 {
188 compatible = "qcom,gcc-ipq4019";
189 #clock-cells = <1>;
190 #power-domain-cells = <1>;
191 #reset-cells = <1>;
199 clock-names = "core";
204 compatible = "qcom,ipq4019-pinctrl";
206 gpio-controller;
207 gpio-ranges = <&tlmm 0 0 100>;
208 #gpio-cells = <2>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
215 compatible = "qcom,vqmmc-ipq4019-regulator";
217 regulator-name = "vqmmc";
218 regulator-min-microvolt = <1500000>;
219 regulator-max-microvolt = <3000000>;
220 regulator-always-on;
225 compatible = "qcom,sdhci-msm-v4";
227 reg-names = "hc", "core";
229 interrupt-names = "hc_irq", "pwr_irq";
230 bus-width = <8>;
233 clock-names = "iface", "core", "xo";
237 blsp_dma: dma-controller@7884000 {
238 compatible = "qcom,bam-v1.7.0";
242 clock-names = "bam_clk";
243 #dma-cells = <1>;
249 compatible = "qcom,spi-qup-v2.2.1";
254 clock-names = "core", "iface";
255 #address-cells = <1>;
256 #size-cells = <0>;
258 dma-names = "tx", "rx";
263 compatible = "qcom,spi-qup-v2.2.1";
268 clock-names = "core", "iface";
269 #address-cells = <1>;
270 #size-cells = <0>;
272 dma-names = "tx", "rx";
277 compatible = "qcom,i2c-qup-v2.2.1";
282 clock-names = "core", "iface";
283 #address-cells = <1>;
284 #size-cells = <0>;
286 dma-names = "tx", "rx";
291 compatible = "qcom,i2c-qup-v2.2.1";
296 clock-names = "core", "iface";
297 #address-cells = <1>;
298 #size-cells = <0>;
300 dma-names = "tx", "rx";
304 cryptobam: dma-controller@8e04000 {
305 compatible = "qcom,bam-v1.7.0";
309 clock-names = "bam_clk";
310 #dma-cells = <1>;
312 qcom,controlled-remotely;
317 compatible = "qcom,crypto-v5.1";
322 clock-names = "iface", "bus", "core";
324 dma-names = "rx", "tx";
328 acc0: clock-controller@b088000 {
329 compatible = "qcom,kpss-acc-v2";
333 acc1: clock-controller@b098000 {
334 compatible = "qcom,kpss-acc-v2";
338 acc2: clock-controller@b0a8000 {
339 compatible = "qcom,kpss-acc-v2";
343 acc3: clock-controller@b0b8000 {
344 compatible = "qcom,kpss-acc-v2";
379 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
385 clock-names = "core", "iface";
387 dma-names = "tx", "rx";
391 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
397 clock-names = "core", "iface";
399 dma-names = "tx", "rx";
403 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
406 timeout-sec = <10>;
416 compatible = "qcom,pcie-ipq4019";
421 reg-names = "dbi", "elbi", "parf", "config";
423 linux,pci-domain = <0>;
424 bus-range = <0x00 0xff>;
425 num-lanes = <1>;
426 #address-cells = <3>;
427 #size-cells = <2>;
433 interrupt-names = "msi";
434 #interrupt-cells = <1>;
435 interrupt-map-mask = <0 0 0 0x7>;
436 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
443 clock-names = "aux",
459 reset-names = "axi_m",
465 "phy",
475 qpic_bam: dma-controller@7984000 {
476 compatible = "qcom,bam-v1.7.0";
480 clock-names = "bam_clk";
481 #dma-cells = <1>;
486 nand: nand-controller@79b0000 {
487 compatible = "qcom,ipq4019-nand";
489 #address-cells = <1>;
490 #size-cells = <0>;
493 clock-names = "core", "aon";
498 dma-names = "tx", "rx", "cmd";
504 nand-ecc-strength = <4>;
505 nand-ecc-step-size = <512>;
506 nand-bus-width = <8>;
511 compatible = "qcom,ipq4019-wifi";
519 reset-names = "wifi_cpu_init", "wifi_radio_srif",
525 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
544 interrupt-names = "msi0", "msi1", "msi2", "msi3",
553 compatible = "qcom,ipq4019-wifi";
561 reset-names = "wifi_cpu_init", "wifi_radio_srif",
567 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
586 interrupt-names = "msi0", "msi1", "msi2", "msi3",
595 #address-cells = <1>;
596 #size-cells = <0>;
597 compatible = "qcom,ipq4019-mdio";
601 ethphy0: ethernet-phy@0 {
605 ethphy1: ethernet-phy@1 {
609 ethphy2: ethernet-phy@2 {
613 ethphy3: ethernet-phy@3 {
617 ethphy4: ethernet-phy@4 {
623 compatible = "qcom,usb-ss-ipq4019-phy";
624 #phy-cells = <0>;
626 reg-names = "phy_base";
628 reset-names = "por_rst";
633 compatible = "qcom,usb-hs-ipq4019-phy";
634 #phy-cells = <0>;
636 reg-names = "phy_base";
638 reset-names = "por_rst", "srif_rst";
643 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
645 #address-cells = <1>;
646 #size-cells = <1>;
650 clock-names = "core", "sleep", "mock_utmi";
659 phy-names = "usb2-phy", "usb3-phy";
665 compatible = "qcom,usb-hs-ipq4019-phy";
666 #phy-cells = <0>;
668 reg-names = "phy_base";
670 reset-names = "por_rst", "srif_rst";
675 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
677 #address-cells = <1>;
678 #size-cells = <1>;
682 clock-names = "master", "sleep", "mock_utmi";
691 phy-names = "usb2-phy";