Lines Matching full:gcc
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
187 gcc: clock-controller@1800000 { label
188 compatible = "qcom,gcc-ipq4019";
198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
231 clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
232 <&gcc GCC_DCD_XO_CLK>;
241 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
252 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
253 <&gcc GCC_BLSP1_AHB_CLK>;
266 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
267 <&gcc GCC_BLSP1_AHB_CLK>;
280 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
281 <&gcc GCC_BLSP1_AHB_CLK>;
294 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
295 <&gcc GCC_BLSP1_AHB_CLK>;
308 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
319 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
320 <&gcc GCC_CRYPTO_AXI_CLK>,
321 <&gcc GCC_CRYPTO_CLK>;
383 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
384 <&gcc GCC_BLSP1_AHB_CLK>;
395 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
396 <&gcc GCC_BLSP1_AHB_CLK>;
440 clocks = <&gcc GCC_PCIE_AHB_CLK>,
441 <&gcc GCC_PCIE_AXI_M_CLK>,
442 <&gcc GCC_PCIE_AXI_S_CLK>;
447 resets = <&gcc PCIE_AXI_M_ARES>,
448 <&gcc PCIE_AXI_S_ARES>,
449 <&gcc PCIE_PIPE_ARES>,
450 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
451 <&gcc PCIE_AXI_S_XPU_ARES>,
452 <&gcc PCIE_PARF_XPU_ARES>,
453 <&gcc PCIE_PHY_ARES>,
454 <&gcc PCIE_AXI_M_STICKY_ARES>,
455 <&gcc PCIE_PIPE_STICKY_ARES>,
456 <&gcc PCIE_PWR_ARES>,
457 <&gcc PCIE_AHB_ARES>,
458 <&gcc PCIE_PHY_AHB_ARES>;
479 clocks = <&gcc GCC_QPIC_CLK>;
491 clocks = <&gcc GCC_QPIC_CLK>,
492 <&gcc GCC_QPIC_AHB_CLK>;
513 resets = <&gcc WIFI0_CPU_INIT_RESET>,
514 <&gcc WIFI0_RADIO_SRIF_RESET>,
515 <&gcc WIFI0_RADIO_WARM_RESET>,
516 <&gcc WIFI0_RADIO_COLD_RESET>,
517 <&gcc WIFI0_CORE_WARM_RESET>,
518 <&gcc WIFI0_CORE_COLD_RESET>;
522 clocks = <&gcc GCC_WCSS2G_CLK>,
523 <&gcc GCC_WCSS2G_REF_CLK>,
524 <&gcc GCC_WCSS2G_RTC_CLK>;
555 resets = <&gcc WIFI1_CPU_INIT_RESET>,
556 <&gcc WIFI1_RADIO_SRIF_RESET>,
557 <&gcc WIFI1_RADIO_WARM_RESET>,
558 <&gcc WIFI1_RADIO_COLD_RESET>,
559 <&gcc WIFI1_CORE_WARM_RESET>,
560 <&gcc WIFI1_CORE_COLD_RESET>;
564 clocks = <&gcc GCC_WCSS5G_CLK>,
565 <&gcc GCC_WCSS5G_REF_CLK>,
566 <&gcc GCC_WCSS5G_RTC_CLK>;
627 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
637 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
647 clocks = <&gcc GCC_USB3_MASTER_CLK>,
648 <&gcc GCC_USB3_SLEEP_CLK>,
649 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
669 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
679 clocks = <&gcc GCC_USB2_MASTER_CLK>,
680 <&gcc GCC_USB2_SLEEP_CLK>,
681 <&gcc GCC_USB2_MOCK_UTMI_CLK>;