Lines Matching refs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
443 clocks = <&gcc GSBI1_H_CLK>;
456 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
468 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
482 clocks = <&gcc GSBI2_H_CLK>;
497 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
510 clocks = <&gcc GSBI3_H_CLK>;
522 clocks = <&gcc GSBI3_QUP_CLK>,
523 <&gcc GSBI3_H_CLK>;
536 clocks = <&gcc GSBI4_H_CLK>;
549 clocks = <&gcc GSBI4_QUP_CLK>,
550 <&gcc GSBI4_H_CLK>;
561 clocks = <&gcc GSBI5_H_CLK>;
572 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
584 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
597 clocks = <&gcc GSBI6_H_CLK>;
608 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
620 clocks = <&gcc GSBI6_QUP_CLK>,
621 <&gcc GSBI6_H_CLK>;
632 clocks = <&gcc GSBI7_H_CLK>;
644 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
656 clocks = <&gcc GSBI7_QUP_CLK>,
657 <&gcc GSBI7_H_CLK>;
666 clocks = <&gcc PRNG_CLK>;
813 gcc: clock-controller@900000 { label
814 compatible = "qcom,gcc-apq8064", "syscon";
843 <&gcc PLL4_VOTE>,
865 <&gcc PLL3>,
866 <&gcc PLL8_VOTE>,
883 compatible = "qcom,kpss-gcc", "syscon";
964 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
966 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
968 resets = <&gcc USB_HS1_RESET>;
995 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
997 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
999 resets = <&gcc USB_HS3_RESET>;
1026 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1028 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1030 resets = <&gcc USB_HS4_RESET>;
1057 clocks = <&gcc SATA_PHY_CFG_CLK>;
1068 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1069 <&gcc SATA_H_CLK>,
1070 <&gcc SATA_A_CLK>,
1071 <&gcc SATA_RXOOB_CLK>,
1072 <&gcc SATA_PMALIVE_CLK>;
1079 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1080 <&gcc SATA_PMALIVE_CLK>;
1093 clocks = <&gcc SDC1_H_CLK>;
1103 clocks = <&gcc SDC3_H_CLK>;
1113 clocks = <&gcc SDC4_H_CLK>;
1133 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1151 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1169 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1444 clocks = <&gcc PCIE_A_CLK>,
1445 <&gcc PCIE_H_CLK>,
1446 <&gcc PCIE_PHY_REF_CLK>;
1448 resets = <&gcc PCIE_ACLK_RESET>,
1449 <&gcc PCIE_HCLK_RESET>,
1450 <&gcc PCIE_POR_RESET>,
1451 <&gcc PCIE_PCI_RESET>,
1452 <&gcc PCIE_PHY_RESET>;