Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
26 no-map;
31 no-map;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 enable-method = "qcom,kpss-acc-v1";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
52 enable-method = "qcom,kpss-acc-v1";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
63 enable-method = "qcom,kpss-acc-v1";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
74 enable-method = "qcom,kpss-acc-v1";
77 next-level-cache = <&L2>;
80 cpu-idle-states = <&CPU_SPC>;
83 L2: l2-cache {
85 cache-level = <2>;
88 idle-states {
90 compatible = "qcom,idle-state-spc",
91 "arm,idle-state";
92 entry-latency-us = <400>;
93 exit-latency-us = <900>;
94 min-residency-us = <3000>;
104 thermal-zones {
105 cpu0-thermal {
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
109 thermal-sensors = <&tsens 7>;
126 cpu1-thermal {
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
130 thermal-sensors = <&tsens 8>;
147 cpu2-thermal {
148 polling-delay-passive = <250>;
149 polling-delay = <1000>;
151 thermal-sensors = <&tsens 9>;
168 cpu3-thermal {
169 polling-delay-passive = <250>;
170 polling-delay = <1000>;
172 thermal-sensors = <&tsens 10>;
190 cpu-pmu {
191 compatible = "qcom,krait-pmu";
197 compatible = "fixed-clock";
198 #clock-cells = <0>;
199 clock-frequency = <19200000>;
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <27000000>;
209 compatible = "fixed-clock";
210 #clock-cells = <0>;
211 clock-frequency = <32768>;
216 compatible = "qcom,sfpb-mutex";
218 #hwlock-cells = <1>;
223 memory-region = <&smem_region>;
231 modem-edge {
235 qcom,smd-edge = <0>;
240 q6-edge {
244 qcom,smd-edge = <1>;
249 dsps-edge {
253 qcom,smd-edge = <3>;
258 riva-edge {
262 qcom,smd-edge = <6>;
271 #address-cells = <1>;
272 #size-cells = <0>;
274 qcom,ipc-1 = <&l2cc 8 4>;
275 qcom,ipc-2 = <&l2cc 8 14>;
276 qcom,ipc-3 = <&l2cc 8 23>;
277 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
281 #qcom,smem-state-cells = <1>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
319 compatible = "qcom,scm-apq8064", "qcom,scm";
322 clock-names = "core";
329 * That is why the ADC is referred to as "HKADC" - HouseKeeping
332 iio-hwmon {
333 compatible = "iio-hwmon";
334 io-channels = <&xoadc 0x00 0x01>, /* Battery */
344 #address-cells = <1>;
345 #size-cells = <1>;
347 compatible = "simple-bus";
350 compatible = "qcom,apq8064-pinctrl";
353 gpio-controller;
354 gpio-ranges = <&tlmm_pinmux 0 0 90>;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&ps_hold>;
369 intc: interrupt-controller@2000000 {
370 compatible = "qcom,msm-qgic2";
371 interrupt-controller;
372 #interrupt-cells = <3>;
378 compatible = "qcom,kpss-timer",
379 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
384 clock-frequency = <27000000>,
386 cpu-offset = <0x80000>;
389 acc0: clock-controller@2088000 {
390 compatible = "qcom,kpss-acc-v1";
394 acc1: clock-controller@2098000 {
395 compatible = "qcom,kpss-acc-v1";
399 acc2: clock-controller@20a8000 {
400 compatible = "qcom,kpss-acc-v1";
404 acc3: clock-controller@20b8000 {
405 compatible = "qcom,kpss-acc-v1";
409 saw0: power-controller@2089000 {
410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 saw1: power-controller@2099000 {
416 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 saw2: power-controller@20a9000 {
422 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 saw3: power-controller@20b9000 {
428 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
433 sps_sic_non_secure: sps-sic-non-secure@12100000 {
440 compatible = "qcom,gsbi-v1.0.0";
441 cell-index = <1>;
444 clock-names = "iface";
445 #address-cells = <1>;
446 #size-cells = <1>;
449 syscon-tcsr = <&tcsr>;
452 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
457 clock-names = "core", "iface";
462 compatible = "qcom,i2c-qup-v1.1.1";
463 pinctrl-0 = <&i2c1_pins>;
464 pinctrl-1 = <&i2c1_pins_sleep>;
465 pinctrl-names = "default", "sleep";
469 clock-names = "core", "iface";
470 #address-cells = <1>;
471 #size-cells = <0>;
479 compatible = "qcom,gsbi-v1.0.0";
480 cell-index = <2>;
483 clock-names = "iface";
484 #address-cells = <1>;
485 #size-cells = <1>;
488 syscon-tcsr = <&tcsr>;
491 compatible = "qcom,i2c-qup-v1.1.1";
493 pinctrl-0 = <&i2c2_pins>;
494 pinctrl-1 = <&i2c2_pins_sleep>;
495 pinctrl-names = "default", "sleep";
498 clock-names = "core", "iface";
499 #address-cells = <1>;
500 #size-cells = <0>;
507 compatible = "qcom,gsbi-v1.0.0";
508 cell-index = <3>;
511 clock-names = "iface";
512 #address-cells = <1>;
513 #size-cells = <1>;
516 compatible = "qcom,i2c-qup-v1.1.1";
517 pinctrl-0 = <&i2c3_pins>;
518 pinctrl-1 = <&i2c3_pins_sleep>;
519 pinctrl-names = "default", "sleep";
524 clock-names = "core", "iface";
525 #address-cells = <1>;
526 #size-cells = <0>;
533 compatible = "qcom,gsbi-v1.0.0";
534 cell-index = <4>;
537 clock-names = "iface";
538 #address-cells = <1>;
539 #size-cells = <1>;
543 compatible = "qcom,i2c-qup-v1.1.1";
544 pinctrl-0 = <&i2c4_pins>;
545 pinctrl-1 = <&i2c4_pins_sleep>;
546 pinctrl-names = "default", "sleep";
551 clock-names = "core", "iface";
558 compatible = "qcom,gsbi-v1.0.0";
559 cell-index = <5>;
562 clock-names = "iface";
563 #address-cells = <1>;
564 #size-cells = <1>;
568 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
573 clock-names = "core", "iface";
578 compatible = "qcom,spi-qup-v1.1.1";
581 pinctrl-0 = <&spi5_default>;
582 pinctrl-1 = <&spi5_sleep>;
583 pinctrl-names = "default", "sleep";
585 clock-names = "core", "iface";
587 #address-cells = <1>;
588 #size-cells = <0>;
594 compatible = "qcom,gsbi-v1.0.0";
595 cell-index = <6>;
598 clock-names = "iface";
599 #address-cells = <1>;
600 #size-cells = <1>;
604 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
609 clock-names = "core", "iface";
614 compatible = "qcom,i2c-qup-v1.1.1";
615 pinctrl-0 = <&i2c6_pins>;
616 pinctrl-1 = <&i2c6_pins_sleep>;
617 pinctrl-names = "default", "sleep";
622 clock-names = "core", "iface";
629 compatible = "qcom,gsbi-v1.0.0";
630 cell-index = <7>;
633 clock-names = "iface";
634 #address-cells = <1>;
635 #size-cells = <1>;
637 syscon-tcsr = <&tcsr>;
640 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
645 clock-names = "core", "iface";
650 compatible = "qcom,i2c-qup-v1.1.1";
651 pinctrl-0 = <&i2c7_pins>;
652 pinctrl-1 = <&i2c7_pins_sleep>;
653 pinctrl-names = "default", "sleep";
658 clock-names = "core", "iface";
667 clock-names = "core";
673 qcom,controller-type = "pmic-arbiter";
677 interrupt-parent = <&tlmm_pinmux>;
679 #interrupt-cells = <2>;
680 interrupt-controller;
681 #address-cells = <1>;
682 #size-cells = <0>;
685 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 gpio-controller;
690 #gpio-cells = <2>;
691 gpio-ranges = <&pm8821_mpps 0 0 4>;
699 qcom,controller-type = "pmic-arbiter";
703 interrupt-parent = <&tlmm_pinmux>;
705 #interrupt-cells = <2>;
706 interrupt-controller;
707 #address-cells = <1>;
708 #size-cells = <0>;
712 compatible = "qcom,pm8921-gpio",
713 "qcom,ssbi-gpio";
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 gpio-controller;
718 gpio-ranges = <&pm8921_gpio 0 0 44>;
719 #gpio-cells = <2>;
724 compatible = "qcom,pm8921-mpp",
725 "qcom,ssbi-mpp";
727 gpio-controller;
728 #gpio-cells = <2>;
729 gpio-ranges = <&pm8921_mpps 0 0 12>;
730 interrupt-controller;
731 #interrupt-cells = <2>;
735 compatible = "qcom,pm8921-rtc";
736 interrupt-parent = <&pmicintc>;
739 allow-set-time;
743 compatible = "qcom,pm8921-pwrkey";
745 interrupt-parent = <&pmicintc>;
748 pull-up;
752 compatible = "qcom,pm8921-adc";
754 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
755 #address-cells = <2>;
756 #size-cells = <0>;
757 #io-channel-cells = <2>;
759 vcoin: adc-channel@0 {
762 vbat: adc-channel@1 {
765 dcin: adc-channel@2 {
768 vph_pwr: adc-channel@4 {
771 batt_therm: adc-channel@8 {
774 batt_id: adc-channel@9 {
777 usb_vbus: adc-channel@a {
780 die_temp: adc-channel@b {
783 ref_625mv: adc-channel@c {
786 ref_1250mv: adc-channel@d {
789 chg_temp: adc-channel@e {
792 ref_muxoff: adc-channel@f {
800 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
802 #address-cells = <1>;
803 #size-cells = <1>;
813 gcc: clock-controller@900000 {
814 compatible = "qcom,gcc-apq8064", "syscon";
816 #clock-cells = <1>;
817 #power-domain-cells = <1>;
818 #reset-cells = <1>;
822 clock-names = "cxo", "pxo", "pll4";
824 tsens: thermal-sensor {
825 compatible = "qcom,msm8960-tsens";
827 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
828 nvmem-cell-names = "calib", "calib_backup";
830 interrupt-names = "uplow";
833 #thermal-sensor-cells = <1>;
837 lcc: clock-controller@28000000 {
838 compatible = "qcom,lcc-apq8064";
840 #clock-cells = <1>;
841 #reset-cells = <1>;
848 clock-names = "pxo",
858 mmcc: clock-controller@4000000 {
859 compatible = "qcom,mmcc-apq8064";
861 #clock-cells = <1>;
862 #power-domain-cells = <1>;
863 #reset-cells = <1>;
872 clock-names = "pxo",
882 l2cc: clock-controller@2011000 {
883 compatible = "qcom,kpss-gcc", "syscon";
888 compatible = "qcom,rpm-apq8064";
895 interrupt-names = "ack", "err", "wakeup";
897 rpmcc: clock-controller {
898 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
899 #clock-cells = <1>;
901 clock-names = "pxo", "cxo";
905 compatible = "qcom,rpm-pm8921-regulators";
949 pm8921_usb_switch: usb-switch {};
951 pm8921_hdmi_switch: hdmi-switch {
952 bias-pull-down;
960 compatible = "qcom,ci-hdrc";
965 clock-names = "core", "iface";
966 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
967 assigned-clock-rates = <60000000>;
969 reset-names = "core";
971 ahb-burst-config = <0>;
973 phy-names = "usb-phy";
975 #reset-cells = <1>;
979 compatible = "qcom,usb-hs-phy-apq8064",
980 "qcom,usb-hs-phy";
982 clock-names = "sleep", "ref";
984 reset-names = "por";
985 #phy-cells = <0>;
991 compatible = "qcom,ci-hdrc";
996 clock-names = "core", "iface";
997 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
998 assigned-clock-rates = <60000000>;
1000 reset-names = "core";
1002 ahb-burst-config = <0>;
1004 phy-names = "usb-phy";
1006 #reset-cells = <1>;
1010 compatible = "qcom,usb-hs-phy-apq8064",
1011 "qcom,usb-hs-phy";
1012 #phy-cells = <0>;
1014 clock-names = "sleep", "ref";
1016 reset-names = "por";
1022 compatible = "qcom,ci-hdrc";
1027 clock-names = "core", "iface";
1028 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1029 assigned-clock-rates = <60000000>;
1031 reset-names = "core";
1033 ahb-burst-config = <0>;
1035 phy-names = "usb-phy";
1037 #reset-cells = <1>;
1041 compatible = "qcom,usb-hs-phy-apq8064",
1042 "qcom,usb-hs-phy";
1043 #phy-cells = <0>;
1045 clock-names = "sleep", "ref";
1047 reset-names = "por";
1053 compatible = "qcom,apq8064-sata-phy";
1056 reg-names = "phy_mem";
1058 clock-names = "cfg";
1059 #phy-cells = <0>;
1063 compatible = "qcom,apq8064-ahci", "generic-ahci";
1073 clock-names = "slave_iface",
1079 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1081 assigned-clock-rates = <100000000>, <100000000>;
1084 phy-names = "sata-phy";
1085 ports-implemented = <0x1>;
1089 sdcc1bam: dma-controller@12402000{
1090 compatible = "qcom,bam-v1.3.0";
1094 clock-names = "bam_clk";
1095 #dma-cells = <1>;
1099 sdcc3bam: dma-controller@12182000{
1100 compatible = "qcom,bam-v1.3.0";
1104 clock-names = "bam_clk";
1105 #dma-cells = <1>;
1109 sdcc4bam: dma-controller@121c2000{
1110 compatible = "qcom,bam-v1.3.0";
1114 clock-names = "bam_clk";
1115 #dma-cells = <1>;
1120 compatible = "simple-bus";
1121 #address-cells = <1>;
1122 #size-cells = <1>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&sdcc1_pins>;
1129 arm,primecell-periphid = <0x00051180>;
1132 interrupt-names = "cmd_irq";
1134 clock-names = "mclk", "apb_pclk";
1135 bus-width = <8>;
1136 max-frequency = <96000000>;
1137 non-removable;
1138 cap-sd-highspeed;
1139 cap-mmc-highspeed;
1141 dma-names = "tx", "rx";
1146 arm,primecell-periphid = <0x00051180>;
1150 interrupt-names = "cmd_irq";
1152 clock-names = "mclk", "apb_pclk";
1153 bus-width = <4>;
1154 cap-sd-highspeed;
1155 cap-mmc-highspeed;
1156 max-frequency = <192000000>;
1157 no-1-8-v;
1159 dma-names = "tx", "rx";
1164 arm,primecell-periphid = <0x00051180>;
1168 interrupt-names = "cmd_irq";
1170 clock-names = "mclk", "apb_pclk";
1171 bus-width = <4>;
1172 cap-sd-highspeed;
1173 cap-mmc-highspeed;
1174 max-frequency = <48000000>;
1176 dma-names = "tx", "rx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&sdc4_gpios>;
1183 compatible = "qcom,tcsr-apq8064", "syscon";
1187 gpu: adreno-3xx@4300000 {
1188 compatible = "qcom,adreno-320.2", "qcom,adreno";
1190 reg-names = "kgsl_3d0_reg_memory";
1192 interrupt-names = "kgsl_3d0_irq";
1193 clock-names =
1269 operating-points-v2 = <&gpu_opp_table>;
1271 gpu_opp_table: opp-table {
1272 compatible = "operating-points-v2";
1274 opp-320000000 {
1275 opp-hz = /bits/ 64 <450000000>;
1278 opp-27000000 {
1279 opp-hz = /bits/ 64 <27000000>;
1290 compatible = "qcom,mdss-dsi-ctrl";
1291 label = "MDSS DSI CTRL->0";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1296 reg-names = "dsi_ctrl";
1305 clock-names = "iface", "bus", "core_mmss",
1309 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1313 assigned-clock-parents = <&dsi0_phy 0>,
1317 syscon-sfpb = <&mmss_sfpb>;
1319 phy-names = "dsi";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1341 dsi0_phy: dsi-phy@4700200 {
1342 compatible = "qcom,dsi-phy-28nm-8960";
1343 #clock-cells = <1>;
1344 #phy-cells = <0>;
1349 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1350 clock-names = "iface", "ref";
1358 compatible = "qcom,apq8064-iommu";
1359 #iommu-cells = <1>;
1360 clock-names =
1374 compatible = "qcom,apq8064-iommu";
1375 #iommu-cells = <1>;
1376 clock-names =
1390 compatible = "qcom,apq8064-iommu";
1391 #iommu-cells = <1>;
1392 clock-names =
1406 compatible = "qcom,apq8064-iommu";
1407 #iommu-cells = <1>;
1408 clock-names =
1422 compatible = "qcom,pcie-apq8064";
1427 reg-names = "dbi", "elbi", "parf", "config";
1429 linux,pci-domain = <0>;
1430 bus-range = <0x00 0xff>;
1431 num-lanes = <1>;
1432 #address-cells = <3>;
1433 #size-cells = <2>;
1437 interrupt-names = "msi";
1438 #interrupt-cells = <1>;
1439 interrupt-map-mask = <0 0 0 0x7>;
1440 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1447 clock-names = "core", "iface", "phy";
1453 reset-names = "axi", "ahb", "por", "pci", "phy";
1457 hdmi: hdmi-tx@4a00000 {
1458 compatible = "qcom,hdmi-tx-8960";
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&hdmi_pinctrl>;
1462 reg-names = "core_physical";
1467 clock-names = "core",
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1491 hdmi_phy: hdmi-phy@4a00400 {
1492 compatible = "qcom,hdmi-phy-8960";
1495 reg-names = "hdmi_phy",
1499 clock-names = "slave_iface";
1500 #phy-cells = <0>;
1513 clock-names = "core_clk",
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1555 riva: riva-pil@3204000 {
1556 compatible = "qcom,riva-pil";
1559 reg-names = "ccu", "dxe", "pmu";
1561 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1563 interrupt-names = "wdog", "fatal";
1565 memory-region = <&wcnss_mem>;
1567 vddcx-supply = <&pm8921_s3>;
1568 vddmx-supply = <&pm8921_l24>;
1569 vddpx-supply = <&pm8921_s4>;
1577 clock-names = "xo";
1579 vddxo-supply = <&pm8921_l4>;
1580 vddrfa-supply = <&pm8921_s2>;
1581 vddpa-supply = <&pm8921_l10>;
1582 vdddig-supply = <&pm8921_lvs2>;
1585 smd-edge {
1589 qcom,smd-edge = <6>;
1595 qcom,smd-channels = "WCNSS_CTRL";
1600 compatible = "qcom,wcnss-bt";
1604 compatible = "qcom,wcnss-wlan";
1608 interrupt-names = "tx", "rx";
1610 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1611 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1618 compatible = "coresight-etb10", "arm,primecell";
1622 clock-names = "apb_pclk";
1624 in-ports {
1627 remote-endpoint = <&replicator_out0>;
1634 compatible = "arm,coresight-tpiu", "arm,primecell";
1638 clock-names = "apb_pclk";
1640 in-ports {
1643 remote-endpoint = <&replicator_out1>;
1650 compatible = "arm,coresight-static-replicator";
1653 clock-names = "apb_pclk";
1655 out-ports {
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1662 remote-endpoint = <&etb_in>;
1668 remote-endpoint = <&tpiu_in>;
1673 in-ports {
1676 remote-endpoint = <&funnel_out>;
1683 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1687 clock-names = "apb_pclk";
1689 in-ports {
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1695 * 2 - connected to STM component
1696 * 3 - not-connected
1697 * 6 - not-connected
1698 * 7 - not-connected
1703 remote-endpoint = <&etm0_out>;
1709 remote-endpoint = <&etm1_out>;
1715 remote-endpoint = <&etm2_out>;
1721 remote-endpoint = <&etm3_out>;
1726 out-ports {
1729 remote-endpoint = <&replicator_in>;
1736 compatible = "arm,coresight-etm3x", "arm,primecell";
1740 clock-names = "apb_pclk";
1744 out-ports {
1747 remote-endpoint = <&funnel_in0>;
1754 compatible = "arm,coresight-etm3x", "arm,primecell";
1758 clock-names = "apb_pclk";
1762 out-ports {
1765 remote-endpoint = <&funnel_in1>;
1772 compatible = "arm,coresight-etm3x", "arm,primecell";
1776 clock-names = "apb_pclk";
1780 out-ports {
1783 remote-endpoint = <&funnel_in4>;
1790 compatible = "arm,coresight-etm3x", "arm,primecell";
1794 clock-names = "apb_pclk";
1798 out-ports {
1801 remote-endpoint = <&funnel_in5>;
1808 #include "qcom-apq8064-pins.dtsi"