Lines Matching +full:0 +full:x002c0000
45 cpu@0 {
57 pinctrl-0 = <&debug_leds>;
63 reg = <0x80000000 0x10000000>; /* 256 MB */
116 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
155 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
163 ti,clock-source = <0x00>; /* timer_sys_ck */
168 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
180 #clock-cells = <0>;
189 pinctrl-0 = <&camera_pins>;
199 data-lanes = <0>;
200 lane-polarity = <0 0>;
201 /* Select strobe = <1> for back camera, <0> for front camera */
213 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
214 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
215 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
216 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
222 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
223 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
229 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
230 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
231 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
239 … OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
240 … OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
241 … OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
244 … OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
245 … OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
246 … OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
247 … OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
248 … OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
249 … OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
250 … OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
251 … OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
257 … OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
258 … OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
264 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
265 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
271 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
272 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
278 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
279 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
285 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
291 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
292 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
293 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
294 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
300 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
301 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
302 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
303 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
304 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
305 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
311 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
312 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
313 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
314 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
315 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
316 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
317 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
318 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
319 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
320 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
326 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
332 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
333 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
334 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
335 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
337 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
338 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
344 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
345 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
351 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
352 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
353 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
354 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
355 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
356 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
357 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
358 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
364 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
365 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
366 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
367 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
368 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
369 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
375 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
376 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
377 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
378 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
379 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
380 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
381 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
382 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
383 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
384 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
385 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
392 pinctrl-0 = <&i2c1_pins>;
397 reg = <0x48>;
410 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
418 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
425 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
432 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
439 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
446 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
454 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
462 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
470 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
500 dma-channel-mask = <0xfffffffc>;
516 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
517 MATRIX_KEY(0x00, 0x01, KEY_O)
518 MATRIX_KEY(0x00, 0x02, KEY_P)
519 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
520 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
521 MATRIX_KEY(0x00, 0x06, KEY_A)
522 MATRIX_KEY(0x00, 0x07, KEY_S)
524 MATRIX_KEY(0x01, 0x00, KEY_W)
525 MATRIX_KEY(0x01, 0x01, KEY_D)
526 MATRIX_KEY(0x01, 0x02, KEY_F)
527 MATRIX_KEY(0x01, 0x03, KEY_G)
528 MATRIX_KEY(0x01, 0x04, KEY_H)
529 MATRIX_KEY(0x01, 0x05, KEY_J)
530 MATRIX_KEY(0x01, 0x06, KEY_K)
531 MATRIX_KEY(0x01, 0x07, KEY_L)
533 MATRIX_KEY(0x02, 0x00, KEY_E)
534 MATRIX_KEY(0x02, 0x01, KEY_DOT)
535 MATRIX_KEY(0x02, 0x02, KEY_UP)
536 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
537 MATRIX_KEY(0x02, 0x05, KEY_Z)
538 MATRIX_KEY(0x02, 0x06, KEY_X)
539 MATRIX_KEY(0x02, 0x07, KEY_C)
540 MATRIX_KEY(0x02, 0x08, KEY_F9)
542 MATRIX_KEY(0x03, 0x00, KEY_R)
543 MATRIX_KEY(0x03, 0x01, KEY_V)
544 MATRIX_KEY(0x03, 0x02, KEY_B)
545 MATRIX_KEY(0x03, 0x03, KEY_N)
546 MATRIX_KEY(0x03, 0x04, KEY_M)
547 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
548 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
549 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
551 MATRIX_KEY(0x04, 0x00, KEY_T)
552 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
553 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
554 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
555 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
556 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
557 MATRIX_KEY(0x04, 0x08, KEY_F10)
559 MATRIX_KEY(0x05, 0x00, KEY_Y)
560 MATRIX_KEY(0x05, 0x08, KEY_F11)
562 MATRIX_KEY(0x06, 0x00, KEY_U)
564 MATRIX_KEY(0x07, 0x00, KEY_I)
565 MATRIX_KEY(0x07, 0x01, KEY_F7)
566 MATRIX_KEY(0x07, 0x02, KEY_F8)
571 ti,pullups = <0x0>;
572 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
577 pinctrl-0 = <&i2c2_pins>;
583 reg = <0x18>;
586 0 /* AIC3X_GPIO1_FUNC_DISABLED */
600 reg = <0x19>;
613 reg = <0x29>;
620 reg = <0x30>;
635 #size-cells = <0>;
637 reg = <0x32>;
638 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
641 led@0 {
642 reg = <0>;
725 reg = <0x55>;
732 reg = <0x60>;
741 reg = <0x63>;
751 reg = <0x6b>;
766 pinctrl-0 = <&i2c3_pins>;
772 reg = <0x1d>;
824 reg = <0x3e>;
828 clocks = <&isp 0>;
840 clock-inv = <0>;
851 reg = <0x0c>;
855 #io-channel-cells = <0>;
861 pinctrl-0 = <&mmc1_pins>;
869 pinctrl-0 = <&mmc2_pins>;
883 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
884 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
886 pinctrl-0 = <&gpmc_pins>;
889 onenand@0,0 {
893 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
900 * cs0 GPMC_CS_CONFIG1: 0xfb001202
901 * cs0 GPMC_CS_CONFIG2: 0x00111100
902 * cs0 GPMC_CS_CONFIG3: 0x00020200
903 * cs0 GPMC_CS_CONFIG4: 0x11001102
904 * cs0 GPMC_CS_CONFIG5: 0x03101616
905 * cs0 GPMC_CS_CONFIG6: 0x90060000
915 gpmc,cs-on-ns = <0>;
918 gpmc,adv-on-ns = <0>;
923 gpmc,we-on-ns = <0>;
929 gpmc,bus-turnaround-ns = <0>;
930 gpmc,cycle2cycle-delay-ns = <0>;
931 gpmc,wait-monitoring-ns = <0>;
941 partition@0 {
943 reg = <0x00000000 0x00020000>;
948 reg = <0x00020000 0x00060000>;
952 reg = <0x00080000 0x00040000>;
956 reg = <0x000c0000 0x00200000>;
960 reg = <0x002c0000 0x00200000>;
964 reg = <0x004c0000 0x0fb40000>;
973 reg = <1 0 0xf>; /* 16 byte IO range */
976 pinctrl-0 = <ðernet_pins>;
980 gpmc,sync-clk-ps = <0>;
981 gpmc,cs-on-ns = <0>;
984 gpmc,adv-on-ns = <0>;
985 gpmc,adv-rd-off-ns = <0>;
986 gpmc,adv-wr-off-ns = <0>;
991 gpmc,page-burst-access-ns = <0>;
995 gpmc,bus-turnaround-ns = <0>;
996 gpmc,cycle2cycle-delay-ns = <0>;
997 gpmc,wait-monitoring-ns = <0>;
998 gpmc,clk-activation-ns = <0>;
999 gpmc,wr-access-ns = <0>;
1011 tsc2005@0 {
1014 reg = <0>;
1038 pinctrl-0 = <&acx565akm_pins>;
1053 pinctrl-0 = <&mcspi4_pins>;
1055 wl1251@0 {
1057 pinctrl-0 = <&wl1251_pins>;
1062 reg = <0>;
1083 interface-type = <0>;
1097 pinctrl-0 = <&uart2_pins>;
1112 pinctrl-0 = <&uart3_pins>;
1119 pinctrl-0 = <&dss_sdi_pins>;
1125 #size-cells = <0>;
1157 pinctrl-0 = <&ssi_pins>;
1165 pinctrl-0 = <&modem_pins>;
1167 hsi-channel-ids = <0>, <1>, <2>, <3>;