Lines Matching +full:0 +full:x10005000
24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
108 reg = <0x10009000 0x60>;
118 reg = <0x10200a80 0x20>;
126 reg = <0x10209000 0x1000>;
133 reg = <0x1020f000 0x100>;
140 reg = <0x10210000 0x1000>;
147 reg = <0x10212000 0x100>;
152 reg = <0x10217000 0x8000>,
153 <0x10005000 0x1000>;
156 gpio-ranges = <&pio 0 0 79>;
169 reg = <0x10310000 0x1000>,
170 <0x10320000 0x1000>,
171 <0x10340000 0x2000>,
172 <0x10360000 0x2000>;
179 reg = <0x10390000 0x1000>;
180 ranges = <0 0x10390000 0x10000>;
185 reg = <0x1000 0x1000>;
191 reg = <0x4000 0x1000>;
197 reg = <0x5000 0x1000>;
202 reg = <0x9000 0x5000>;
214 reg = <0x11002000 0x400>;
225 reg = <0x11003000 0x400>;
236 reg = <0x11004000 0x400>;
246 reg = <0x11006000 0x1000>;
261 reg = <0x11007000 0x90>,
262 <0x11000100 0x80>;
271 #size-cells = <0>;
279 #size-cells = <0>;
280 reg = <0x1100a000 0x100>;
292 reg = <0x11014000 0xe0>;
297 #size-cells = <0>;
303 reg = <0x1a000000 0x1000>;
311 reg = <0x1a0c0000 0x01000>,
312 <0x1a0c3e00 0x0100>;
337 ranges = <0 0x1a0c4000 0xe00>;
340 u2port0: usb-phy@0 {
341 reg = <0 0x700>;
349 reg = <0x700 0x700>;
359 reg = <0x1a100800 0x1000>;
366 reg = <0x1a140000 0x1000>;
372 reg = <0x1a145000 0x1000>;
397 bus-range = <0x00 0xff>;
398 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
402 interrupt-map-mask = <0 0 0 7>;
403 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
404 <0 0 0 2 &pcie_intc1 1>,
405 <0 0 0 3 &pcie_intc1 2>,
406 <0 0 0 4 &pcie_intc1 3>;
409 #address-cells = <0>;
419 ranges = <0 0x1a14a000 0x1000>;
422 pcieport1: pcie-phy@0 {
423 reg = <0 0x1000>;
433 reg = <0x1b000000 0x1000>;
440 reg = <0x1b100000 0x20000>;
476 #size-cells = <0>;
482 reg = <0x1b128000 0x3000>;
488 reg = <0x1b130000 0x3000>;