Lines Matching +full:mtk +full:- +full:xhci
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
18 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
78 compatible = "arm,cortex-a7";
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
90 compatible = "arm,cortex-a7";
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
102 compatible = "arm,cortex-a7";
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
114 compatible = "arm,cortex-a7";
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
126 compatible = "arm,cortex-a7-pmu";
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
159 thermal-sensors = <&thermal 0>;
162 cpu_passive: cpu-passive {
168 cpu_active: cpu-active {
174 cpu_hot: cpu-hot {
180 cpu-crit {
187 cooling-maps {
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
231 #clock-cells = <1>;
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
239 #clock-cells = <1>;
240 #reset-cells = <1>;
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
248 #clock-cells = <1>;
249 #reset-cells = <1>;
253 compatible = "mediatek,mt7623-pinctrl";
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 pins-are-numbered;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 #interrupt-cells = <2>;
267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
271 scpsys: power-controller@10006000 {
272 compatible = "mediatek,mt7623-scpsys",
273 "mediatek,mt2701-scpsys",
275 #power-domain-cells = <1>;
281 clock-names = "mm", "mfg", "ethif";
285 compatible = "mediatek,mt7623-wdt",
286 "mediatek,mt6589-wdt";
291 compatible = "mediatek,mt7623-timer",
292 "mediatek,mt6577-timer";
296 clock-names = "system-clk", "rtc-clk";
300 compatible = "mediatek,mt7623-pwrap",
301 "mediatek,mt2701-pwrap";
303 reg-names = "pwrap";
306 reset-names = "pwrap";
309 clock-names = "spi", "wrap";
313 compatible = "mediatek,mt7623-cir";
317 clock-names = "clk";
321 sysirq: interrupt-controller@10200100 {
322 compatible = "mediatek,mt7623-sysirq",
323 "mediatek,mt6577-sysirq";
324 interrupt-controller;
325 #interrupt-cells = <3>;
326 interrupt-parent = <&gic>;
331 compatible = "mediatek,mt7623-efuse",
332 "mediatek,mt8173-efuse";
334 #address-cells = <1>;
335 #size-cells = <1>;
342 compatible = "mediatek,mt7623-apmixedsys",
343 "mediatek,mt2701-apmixedsys",
346 #clock-cells = <1>;
350 compatible = "mediatek,mt7623-rng";
353 clock-names = "rng";
356 gic: interrupt-controller@10211000 {
357 compatible = "arm,cortex-a7-gic";
358 interrupt-controller;
359 #interrupt-cells = <3>;
360 interrupt-parent = <&gic>;
368 compatible = "mediatek,mt7623-auxadc",
369 "mediatek,mt2701-auxadc";
372 clock-names = "main";
373 #io-channel-cells = <1>;
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
383 clock-names = "baud", "bus";
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
394 clock-names = "baud", "bus";
399 compatible = "mediatek,mt7623-uart",
400 "mediatek,mt6577-uart";
405 clock-names = "baud", "bus";
410 compatible = "mediatek,mt7623-uart",
411 "mediatek,mt6577-uart";
416 clock-names = "baud", "bus";
421 compatible = "mediatek,mt7623-pwm";
423 #pwm-cells = <2>;
431 clock-names = "top", "main", "pwm1", "pwm2",
437 compatible = "mediatek,mt7623-i2c",
438 "mediatek,mt6577-i2c";
442 clock-div = <16>;
445 clock-names = "main", "dma";
446 #address-cells = <1>;
447 #size-cells = <0>;
452 compatible = "mediatek,mt7623-i2c",
453 "mediatek,mt6577-i2c";
457 clock-div = <16>;
460 clock-names = "main", "dma";
461 #address-cells = <1>;
462 #size-cells = <0>;
467 compatible = "mediatek,mt7623-i2c",
468 "mediatek,mt6577-i2c";
472 clock-div = <16>;
475 clock-names = "main", "dma";
476 #address-cells = <1>;
477 #size-cells = <0>;
482 compatible = "mediatek,mt7623-spi",
483 "mediatek,mt2701-spi";
484 #address-cells = <1>;
485 #size-cells = <0>;
491 clock-names = "parent-clk", "sel-clk", "spi-clk";
496 #thermal-sensor-cells = <1>;
497 compatible = "mediatek,mt7623-thermal",
498 "mediatek,mt2701-thermal";
502 clock-names = "therm", "auxadc";
504 reset-names = "therm";
507 nvmem-cells = <&thermal_calibration_data>;
508 nvmem-cell-names = "calibration-data";
512 compatible = "mediatek,mt7623-btif",
513 "mediatek,mtk-btif";
517 clock-names = "main";
518 reg-shift = <2>;
519 reg-io-width = <4>;
524 compatible = "mediatek,mt7623-nfc",
525 "mediatek,mt2701-nfc";
528 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
531 clock-names = "nfi_clk", "pad_clk";
533 ecc-engine = <&bch>;
534 #address-cells = <1>;
535 #size-cells = <0>;
539 compatible = "mediatek,mt7623-ecc",
540 "mediatek,mt2701-ecc";
544 clock-names = "nfiecc_clk";
549 compatible = "mediatek,mt7623-nor",
550 "mediatek,mt8173-nor";
554 clock-names = "spi", "sf";
555 #address-cells = <1>;
556 #size-cells = <0>;
561 compatible = "mediatek,mt7623-spi",
562 "mediatek,mt2701-spi";
563 #address-cells = <1>;
564 #size-cells = <0>;
570 clock-names = "parent-clk", "sel-clk", "spi-clk";
575 compatible = "mediatek,mt7623-spi",
576 "mediatek,mt2701-spi";
577 #address-cells = <1>;
578 #size-cells = <0>;
584 clock-names = "parent-clk", "sel-clk", "spi-clk";
589 compatible = "mediatek,mt7623-musb",
590 "mediatek,mtk-musb";
593 interrupt-names = "mc";
599 clock-names = "main","mcu","univpll";
600 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
604 u2phy1: t-phy@11210000 {
605 compatible = "mediatek,mt7623-tphy",
606 "mediatek,generic-tphy-v1";
608 #address-cells = <2>;
609 #size-cells = <2>;
613 u2port2: usb-phy@11210800 {
616 clock-names = "ref";
617 #phy-cells = <1>;
621 audsys: clock-controller@11220000 {
622 compatible = "mediatek,mt7623-audsys",
623 "mediatek,mt2701-audsys",
626 #clock-cells = <1>;
628 afe: audio-controller {
629 compatible = "mediatek,mt7623-audio",
630 "mediatek,mt2701-audio";
633 interrupt-names = "afe", "asys";
634 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
671 clock-names = "infra_sys_audio_clk",
706 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
710 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
712 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
717 compatible = "mediatek,mt7623-mmc",
718 "mediatek,mt2701-mmc";
723 clock-names = "source", "hclk";
728 compatible = "mediatek,mt7623-mmc",
729 "mediatek,mt2701-mmc";
734 clock-names = "source", "hclk";
739 compatible = "mediatek,mt7623-vdecsys",
740 "mediatek,mt2701-vdecsys",
743 #clock-cells = <1>;
747 compatible = "mediatek,mt7623-hifsys",
748 "mediatek,mt2701-hifsys",
751 #clock-cells = <1>;
752 #reset-cells = <1>;
756 compatible = "mediatek,mt7623-pcie";
762 reg-names = "subsys", "port0", "port1", "port2";
763 #address-cells = <3>;
764 #size-cells = <2>;
765 #interrupt-cells = <1>;
766 interrupt-map-mask = <0xf800 0 0 0>;
767 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
774 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
778 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
782 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
783 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
784 bus-range = <0x00 0xff>;
791 #address-cells = <3>;
792 #size-cells = <2>;
793 #interrupt-cells = <1>;
794 interrupt-map-mask = <0 0 0 0>;
795 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
802 #address-cells = <3>;
803 #size-cells = <2>;
804 #interrupt-cells = <1>;
805 interrupt-map-mask = <0 0 0 0>;
806 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
813 #address-cells = <3>;
814 #size-cells = <2>;
815 #interrupt-cells = <1>;
816 interrupt-map-mask = <0 0 0 0>;
817 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
823 pcie0_phy: t-phy@1a149000 {
824 compatible = "mediatek,mt7623-tphy",
825 "mediatek,generic-tphy-v1";
827 #address-cells = <2>;
828 #size-cells = <2>;
832 pcie0_port: pcie-phy@1a149900 {
835 clock-names = "ref";
836 #phy-cells = <1>;
841 pcie1_phy: t-phy@1a14a000 {
842 compatible = "mediatek,mt7623-tphy",
843 "mediatek,generic-tphy-v1";
845 #address-cells = <2>;
846 #size-cells = <2>;
850 pcie1_port: pcie-phy@1a14a900 {
853 clock-names = "ref";
854 #phy-cells = <1>;
860 compatible = "mediatek,mt7623-xhci",
861 "mediatek,mtk-xhci";
864 reg-names = "mac", "ippc";
868 clock-names = "sys_ck", "ref_ck";
869 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
874 u3phy1: t-phy@1a1c4000 {
875 compatible = "mediatek,mt7623-tphy",
876 "mediatek,generic-tphy-v1";
878 #address-cells = <2>;
879 #size-cells = <2>;
883 u2port0: usb-phy@1a1c4800 {
886 clock-names = "ref";
887 #phy-cells = <1>;
891 u3port0: usb-phy@1a1c4900 {
894 clock-names = "ref";
895 #phy-cells = <1>;
901 compatible = "mediatek,mt7623-xhci",
902 "mediatek,mtk-xhci";
905 reg-names = "mac", "ippc";
909 clock-names = "sys_ck", "ref_ck";
910 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
915 u3phy2: t-phy@1a244000 {
916 compatible = "mediatek,mt7623-tphy",
917 "mediatek,generic-tphy-v1";
919 #address-cells = <2>;
920 #size-cells = <2>;
924 u2port1: usb-phy@1a244800 {
927 clock-names = "ref";
928 #phy-cells = <1>;
932 u3port1: usb-phy@1a244900 {
935 clock-names = "ref";
936 #phy-cells = <1>;
942 compatible = "mediatek,mt7623-ethsys",
943 "mediatek,mt2701-ethsys",
946 #clock-cells = <1>;
947 #reset-cells = <1>;
950 hsdma: dma-controller@1b007000 {
951 compatible = "mediatek,mt7623-hsdma";
955 clock-names = "hsdma";
956 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
957 #dma-cells = <1>;
961 compatible = "mediatek,mt7623-eth",
962 "mediatek,mt2701-eth",
973 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
977 reset-names = "fe", "gmac", "ppe";
978 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
981 #address-cells = <1>;
982 #size-cells = <0>;
987 compatible = "mediatek,eip97-crypto";
995 clock-names = "cryp";
996 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1001 compatible = "mediatek,mt7623-bdpsys",
1002 "mediatek,mt2701-bdpsys",
1005 #clock-cells = <1>;
1010 cir_pins_a:cir-default {
1011 pins-cir {
1013 bias-disable;
1017 i2c0_pins_a: i2c0-default {
1018 pins-i2c0 {
1021 bias-disable;
1025 i2c1_pins_a: i2c1-default {
1026 pin-i2c1 {
1029 bias-disable;
1033 i2c1_pins_b: i2c1-alt {
1034 pin-i2c1 {
1037 bias-disable;
1041 i2c2_pins_a: i2c2-default {
1042 pin-i2c2 {
1045 bias-disable;
1049 i2c2_pins_b: i2c2-alt {
1050 pin-i2c2 {
1053 bias-disable;
1057 i2s0_pins_a: i2s0-default {
1058 pin-i2s0 {
1064 drive-strength = <MTK_DRIVE_12mA>;
1065 bias-pull-down;
1069 i2s1_pins_a: i2s1-default {
1070 pin-i2s1 {
1076 drive-strength = <MTK_DRIVE_12mA>;
1077 bias-pull-down;
1081 key_pins_a: keys-alt {
1082 pins-keys {
1085 input-enable;
1089 led_pins_a: leds-alt {
1090 pins-leds {
1098 pins-cmd-dat {
1108 input-enable;
1109 bias-pull-up;
1112 pins-clk {
1114 bias-pull-down;
1117 pins-rst {
1119 bias-pull-up;
1124 pins-cmd-dat {
1134 input-enable;
1135 drive-strength = <MTK_DRIVE_2mA>;
1136 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1139 pins-clk {
1141 drive-strength = <MTK_DRIVE_2mA>;
1142 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1145 pins-rst {
1147 bias-pull-up;
1152 pins-cmd-dat {
1158 input-enable;
1159 drive-strength = <MTK_DRIVE_4mA>;
1160 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1163 pins-clk {
1165 bias-pull-down;
1166 drive-strength = <MTK_DRIVE_4mA>;
1169 pins-wp {
1171 input-enable;
1172 bias-pull-up;
1175 pins-insert {
1177 bias-pull-up;
1182 pins-cmd-dat {
1188 input-enable;
1189 drive-strength = <MTK_DRIVE_4mA>;
1190 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1193 pins-clk {
1195 drive-strength = <MTK_DRIVE_4mA>;
1196 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1201 pins-ale {
1203 drive-strength = <MTK_DRIVE_8mA>;
1204 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1207 pins-dat {
1217 input-enable;
1218 drive-strength = <MTK_DRIVE_8mA>;
1219 bias-pull-up;
1222 pins-we {
1224 drive-strength = <MTK_DRIVE_8mA>;
1225 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1233 bias-disable;
1237 pwm_pins_a: pwm-default {
1238 pins-pwm {
1247 spi0_pins_a: spi0-default {
1248 pins-spi {
1253 bias-disable;
1257 spi1_pins_a: spi1-default {
1258 pins-spi {
1266 spi2_pins_a: spi2-default {
1267 pins-spi {
1275 uart0_pins_a: uart0-default {
1276 pins-dat {
1282 uart1_pins_a: uart1-default {
1283 pins-dat {
1289 uart2_pins_a: uart2-default {
1290 pins-dat {
1296 uart2_pins_b: uart2-alt {
1297 pins-dat {