Lines Matching +full:jpgdec +full:- +full:smi
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
19 #size-cells = <2>;
21 interrupt-parent = <&cirq>;
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "mediatek,mt81xx-tz-smp";
30 compatible = "arm,cortex-a7";
35 compatible = "arm,cortex-a7";
40 compatible = "arm,cortex-a7";
45 compatible = "arm,cortex-a7";
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
55 trustzone-bootinfo@80002000 {
56 compatible = "mediatek,trustzone-bootinfo";
62 compatible = "fixed-clock";
63 clock-frequency = <13000000>;
64 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <32000>;
70 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <26000000>;
77 clock-output-names = "clk26m";
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32000>;
84 clock-output-names = "rtc32k";
87 thermal-zones {
89 polling-delay-passive = <1000>; /* milliseconds */
90 polling-delay = <1000>; /* milliseconds */
92 thermal-sensors = <&thermal 0>;
93 sustainable-power = <1000>;
96 threshold: trip-point@0 {
102 target: trip-point@1 {
118 compatible = "arm,armv7-timer";
119 interrupt-parent = <&gic>;
127 compatible = "mediatek,mt2701-topckgen", "syscon";
129 #clock-cells = <1>;
133 compatible = "mediatek,mt2701-infracfg", "syscon";
135 #clock-cells = <1>;
136 #reset-cells = <1>;
140 compatible = "mediatek,mt2701-pericfg", "syscon";
142 #clock-cells = <1>;
143 #reset-cells = <1>;
147 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
151 scpsys: power-controller@10006000 {
152 compatible = "mediatek,mt2701-scpsys", "syscon";
153 #power-domain-cells = <1>;
159 clock-names = "mm", "mfg", "ethif";
163 compatible = "mediatek,mt2701-wdt",
164 "mediatek,mt6589-wdt";
169 compatible = "mediatek,mt2701-timer",
170 "mediatek,mt6577-timer";
174 clock-names = "system-clk", "rtc-clk";
178 compatible = "mediatek,mt2701-pinctrl";
180 mediatek,pctl-regmap = <&syscfg_pctl_a>;
181 pins-are-numbered;
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
190 smi_common: smi@1000c000 {
191 compatible = "mediatek,mt2701-smi-common";
196 clock-names = "apb", "smi", "async";
197 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
200 sysirq: interrupt-controller@10200100 {
201 compatible = "mediatek,mt2701-sysirq",
202 "mediatek,mt6577-sysirq";
203 interrupt-controller;
204 #interrupt-cells = <3>;
205 interrupt-parent = <&gic>;
209 cirq: interrupt-controller@10204000 {
210 compatible = "mediatek,mt2701-cirq",
211 "mediatek,mtk-cirq";
212 interrupt-controller;
213 #interrupt-cells = <3>;
214 interrupt-parent = <&sysirq>;
216 mediatek,ext-irq-range = <32 200>;
220 compatible = "mediatek,mt2701-m4u";
224 clock-names = "bclk";
226 #iommu-cells = <1>;
230 compatible = "mediatek,mt2701-apmixedsys", "syscon";
232 #clock-cells = <1>;
235 gic: interrupt-controller@10211000 {
236 compatible = "arm,cortex-a7-gic";
237 interrupt-controller;
238 #interrupt-cells = <3>;
239 interrupt-parent = <&gic>;
247 compatible = "mediatek,mt2701-auxadc";
250 clock-names = "main";
251 #io-channel-cells = <1>;
256 compatible = "mediatek,mt2701-uart",
257 "mediatek,mt6577-uart";
261 clock-names = "baud", "bus";
266 compatible = "mediatek,mt2701-uart",
267 "mediatek,mt6577-uart";
271 clock-names = "baud", "bus";
276 compatible = "mediatek,mt2701-uart",
277 "mediatek,mt6577-uart";
281 clock-names = "baud", "bus";
286 compatible = "mediatek,mt2701-uart",
287 "mediatek,mt6577-uart";
291 clock-names = "baud", "bus";
296 compatible = "mediatek,mt2701-i2c",
297 "mediatek,mt6577-i2c";
301 clock-div = <16>;
303 clock-names = "main", "dma";
304 #address-cells = <1>;
305 #size-cells = <0>;
310 compatible = "mediatek,mt2701-i2c",
311 "mediatek,mt6577-i2c";
315 clock-div = <16>;
317 clock-names = "main", "dma";
318 #address-cells = <1>;
319 #size-cells = <0>;
324 compatible = "mediatek,mt2701-i2c",
325 "mediatek,mt6577-i2c";
329 clock-div = <16>;
331 clock-names = "main", "dma";
332 #address-cells = <1>;
333 #size-cells = <0>;
338 compatible = "mediatek,mt2701-spi";
339 #address-cells = <1>;
340 #size-cells = <0>;
346 clock-names = "parent-clk", "sel-clk", "spi-clk";
351 #thermal-sensor-cells = <0>;
352 compatible = "mediatek,mt2701-thermal";
356 clock-names = "therm", "auxadc";
358 reset-names = "therm";
364 compatible = "mediatek,mt2701-nfc";
369 clock-names = "nfi_clk", "pad_clk";
371 ecc-engine = <&bch>;
372 #address-cells = <1>;
373 #size-cells = <0>;
377 compatible = "mediatek,mt2701-ecc";
381 clock-names = "nfiecc_clk";
386 compatible = "mediatek,mt2701-nor",
387 "mediatek,mt8173-nor";
391 clock-names = "spi", "sf";
392 #address-cells = <1>;
393 #size-cells = <0>;
398 compatible = "mediatek,mt2701-spi";
399 #address-cells = <1>;
400 #size-cells = <0>;
406 clock-names = "parent-clk", "sel-clk", "spi-clk";
411 compatible = "mediatek,mt2701-spi";
412 #address-cells = <1>;
413 #size-cells = <0>;
419 clock-names = "parent-clk", "sel-clk", "spi-clk";
423 audsys: clock-controller@11220000 {
424 compatible = "mediatek,mt2701-audsys", "syscon";
426 #clock-cells = <1>;
428 afe: audio-controller {
429 compatible = "mediatek,mt2701-audio";
432 interrupt-names = "afe", "asys";
433 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
470 clock-names = "infra_sys_audio_clk",
505 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
509 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
511 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
516 compatible = "mediatek,mt2701-mmsys", "syscon";
518 #clock-cells = <1>;
522 compatible = "mediatek,mt2701-disp-pwm";
524 #pwm-cells = <2>;
526 clock-names = "main", "mm";
531 compatible = "mediatek,mt2701-smi-larb";
533 mediatek,smi = <&smi_common>;
534 mediatek,larb-id = <0>;
537 clock-names = "apb", "smi";
538 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
542 compatible = "mediatek,mt2701-imgsys", "syscon";
544 #clock-cells = <1>;
548 compatible = "mediatek,mt2701-smi-larb";
550 mediatek,smi = <&smi_common>;
551 mediatek,larb-id = <2>;
554 clock-names = "apb", "smi";
555 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
559 compatible = "mediatek,mt2701-jpgdec";
564 clock-names = "jpgdec-smi",
565 "jpgdec";
566 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
572 compatible = "mediatek,mt2701-jpgenc",
573 "mediatek,mtk-jpgenc";
577 clock-names = "jpgenc";
578 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
584 compatible = "mediatek,mt2701-vdecsys", "syscon";
586 #clock-cells = <1>;
590 compatible = "mediatek,mt2701-smi-larb";
592 mediatek,smi = <&smi_common>;
593 mediatek,larb-id = <1>;
596 clock-names = "apb", "smi";
597 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
601 compatible = "mediatek,mt2701-hifsys", "syscon";
603 #clock-cells = <1>;
604 #reset-cells = <1>;
608 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
611 reg-names = "mac", "ippc";
615 clock-names = "sys_ck", "ref_ck";
616 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
621 u3phy0: t-phy@1a1c4000 {
622 compatible = "mediatek,mt2701-tphy",
623 "mediatek,generic-tphy-v1";
625 #address-cells = <2>;
626 #size-cells = <2>;
630 u2port0: usb-phy@1a1c4800 {
633 clock-names = "ref";
634 #phy-cells = <1>;
638 u3port0: usb-phy@1a1c4900 {
641 clock-names = "ref";
642 #phy-cells = <1>;
648 compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
651 reg-names = "mac", "ippc";
655 clock-names = "sys_ck", "ref_ck";
656 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
661 u3phy1: t-phy@1a244000 {
662 compatible = "mediatek,mt2701-tphy",
663 "mediatek,generic-tphy-v1";
665 #address-cells = <2>;
666 #size-cells = <2>;
670 u2port1: usb-phy@1a244800 {
673 clock-names = "ref";
674 #phy-cells = <1>;
678 u3port1: usb-phy@1a244900 {
681 clock-names = "ref";
682 #phy-cells = <1>;
688 compatible = "mediatek,mt2701-musb",
689 "mediatek,mtk-musb";
692 interrupt-names = "mc";
698 clock-names = "main","mcu","univpll";
699 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
703 u2phy0: t-phy@11210000 {
704 compatible = "mediatek,mt2701-tphy",
705 "mediatek,generic-tphy-v1";
707 #address-cells = <2>;
708 #size-cells = <2>;
712 u2port2: usb-phy@1a1c4800 {
715 clock-names = "ref";
716 #phy-cells = <1>;
722 compatible = "mediatek,mt2701-ethsys", "syscon";
724 #clock-cells = <1>;
725 #reset-cells = <1>;
729 compatible = "mediatek,mt2701-eth", "syscon";
739 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
743 reset-names = "fe", "gmac", "ppe";
744 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
747 #address-cells = <1>;
748 #size-cells = <0>;
753 compatible = "mediatek,mt2701-bdpsys", "syscon";
755 #clock-cells = <1>;