Lines Matching +full:cortex +full:- +full:a8
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
28 enable-method = "amlogic,meson8-smp";
30 operating-points-v2 = <&cpu_opp_table>;
32 #cooling-cells = <2>; /* min followed by max */
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
40 enable-method = "amlogic,meson8-smp";
42 operating-points-v2 = <&cpu_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
52 enable-method = "amlogic,meson8-smp";
54 operating-points-v2 = <&cpu_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
61 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
64 enable-method = "amlogic,meson8-smp";
66 operating-points-v2 = <&cpu_opp_table>;
68 #cooling-cells = <2>; /* min followed by max */
72 cpu_opp_table: opp-table {
73 compatible = "operating-points-v2";
74 opp-shared;
76 opp-96000000 {
77 opp-hz = /bits/ 64 <96000000>;
78 opp-microvolt = <825000>;
80 opp-192000000 {
81 opp-hz = /bits/ 64 <192000000>;
82 opp-microvolt = <825000>;
84 opp-312000000 {
85 opp-hz = /bits/ 64 <312000000>;
86 opp-microvolt = <825000>;
88 opp-408000000 {
89 opp-hz = /bits/ 64 <408000000>;
90 opp-microvolt = <825000>;
92 opp-504000000 {
93 opp-hz = /bits/ 64 <504000000>;
94 opp-microvolt = <825000>;
96 opp-600000000 {
97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <850000>;
100 opp-720000000 {
101 opp-hz = /bits/ 64 <720000000>;
102 opp-microvolt = <850000>;
104 opp-816000000 {
105 opp-hz = /bits/ 64 <816000000>;
106 opp-microvolt = <875000>;
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <925000>;
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <975000>;
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <1025000>;
120 opp-1608000000 {
121 opp-hz = /bits/ 64 <1608000000>;
122 opp-microvolt = <1100000>;
124 opp-1800000000 {
126 opp-hz = /bits/ 64 <1800000000>;
127 opp-microvolt = <1125000>;
129 opp-1992000000 {
131 opp-hz = /bits/ 64 <1992000000>;
132 opp-microvolt = <1150000>;
136 gpu_opp_table: gpu-opp-table {
137 compatible = "operating-points-v2";
139 opp-182142857 {
140 opp-hz = /bits/ 64 <182142857>;
141 opp-microvolt = <1150000>;
143 opp-318750000 {
144 opp-hz = /bits/ 64 <318750000>;
145 opp-microvolt = <1150000>;
147 opp-425000000 {
148 opp-hz = /bits/ 64 <425000000>;
149 opp-microvolt = <1150000>;
151 opp-510000000 {
152 opp-hz = /bits/ 64 <510000000>;
153 opp-microvolt = <1150000>;
155 opp-637500000 {
156 opp-hz = /bits/ 64 <637500000>;
157 opp-microvolt = <1150000>;
158 turbo-mode;
163 compatible = "arm,cortex-a9-pmu";
168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
171 reserved-memory {
172 #address-cells = <1>;
173 #size-cells = <1>;
179 no-map;
185 * piece of ARC code ("arc_power" in the vendor u-boot tree)
189 * simply the power key) and re-starts the ARM core once it
192 power-firmware@4f00000 {
194 no-map;
198 thermal-zones {
200 polling-delay-passive = <250>; /* milliseconds */
201 polling-delay = <1000>; /* milliseconds */
202 thermal-sensors = <&thermal_sensor>;
204 cooling-maps {
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 soc_passive: soc-passive {
231 soc_hot: soc-hot {
237 soc_critical: soc-critical {
247 compatible = "simple-bus";
249 #address-cells = <1>;
250 #size-cells = <1>;
253 ddr_clkc: clock-controller@400 {
254 compatible = "amlogic,meson8-ddr-clkc";
257 clock-names = "xtal";
258 #clock-cells = <1>;
262 compatible = "simple-bus";
264 #address-cells = <1>;
265 #size-cells = <1>;
268 canvas: video-lut@20 {
269 compatible = "amlogic,meson8-canvas",
277 compatible = "simple-bus";
279 #address-cells = <1>;
280 #size-cells = <1>;
284 compatible = "amlogic,meson8-mali", "arm,mali-450";
302 interrupt-names = "gp", "gpmmu", "pp", "pmu",
309 clock-names = "bus", "core";
311 assigned-clocks = <&clkc CLKID_MALI>;
312 assigned-clock-rates = <318750000>;
314 operating-points-v2 = <&gpu_opp_table>;
315 #cooling-cells = <2>; /* min followed by max */
321 compatible = "amlogic,aiu-meson8", "amlogic,aiu";
331 clock-names = "pclk",
345 compatible = "amlogic,meson8-pmu", "syscon";
350 compatible = "amlogic,meson8-aobus-pinctrl";
352 #address-cells = <1>;
353 #size-cells = <1>;
356 gpio_ao: ao-bank@14 {
360 reg-names = "mux", "pull", "gpio";
361 gpio-controller;
362 #gpio-cells = <2>;
363 gpio-ranges = <&pinctrl_aobus 0 0 16>;
366 i2s_am_clk_pins: i2s-am-clk-out {
370 bias-disable;
374 i2s_out_ao_clk_pins: i2s-ao-clk-out {
378 bias-disable;
382 i2s_out_lr_clk_pins: i2s-lr-clk-out {
386 bias-disable;
390 i2s_out_ch01_ao_pins: i2s-out-ch01 {
394 bias-disable;
402 bias-disable;
410 bias-disable;
418 bias-disable;
422 pwm_f_ao_pins: pwm-f-ao {
426 bias-disable;
433 compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
441 reset: reset-controller@4404 {
442 compatible = "amlogic,meson8b-reset";
444 #reset-cells = <1>;
447 analog_top: analog-top@81a8 {
448 compatible = "amlogic,meson8-analog-top", "syscon";
453 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
455 #pwm-cells = <3>;
459 clock-measure@8758 {
460 compatible = "amlogic,meson8-clk-measure";
465 compatible = "amlogic,meson8-cbus-pinctrl";
467 #address-cells = <1>;
468 #size-cells = <1>;
476 reg-names = "mux", "pull", "pull-enable", "gpio";
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = <&pinctrl_cbus 0 0 120>;
482 sd_a_pins: sd-a {
487 bias-disable;
491 sd_b_pins: sd-b {
496 bias-disable;
500 sd_c_pins: sd-c {
505 bias-disable;
509 sdxc_b_pins: sdxc-b {
514 bias-pull-up;
518 spdif_out_pins: spdif-out {
522 bias-disable;
530 bias-disable;
542 bias-disable;
546 pwm_e_pins: pwm-e {
550 bias-disable;
554 uart_a1_pins: uart-a1 {
559 bias-disable;
563 uart_a1_cts_rts_pins: uart-a1-cts-rts {
568 bias-disable;
575 ao_arc_sram: ao-arc-sram@0 {
576 compatible = "amlogic,meson8-ao-arc-sram";
581 smp-sram@1ff80 {
582 compatible = "amlogic,meson8-smp-sram";
588 compatible = "amlogic,meson8-efuse";
590 clock-names = "core";
600 clock-names = "stmmaceth";
602 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
606 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
611 clkc: clock-controller {
612 compatible = "amlogic,meson8-clkc";
614 clock-names = "xtal", "ddr_pll";
615 #clock-cells = <1>;
616 #reset-cells = <1>;
619 pwrc: power-controller {
620 compatible = "amlogic,meson8-pwrc";
621 #power-domain-cells = <1>;
622 amlogic,ao-sysctrl = <&pmu>;
624 clock-names = "vpu";
625 assigned-clocks = <&clkc CLKID_VPU>;
626 assigned-clock-rates = <364285714>;
631 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
633 clock-names = "core";
649 arm,data-latency = <3 3 3>;
650 arm,tag-latency = <2 2 2>;
651 arm,filter-ranges = <0x100000 0xc0000000>;
652 prefetch-data = <1>;
653 prefetch-instr = <1>;
654 arm,shared-override;
659 compatible = "arm,cortex-a9-scu";
664 compatible = "arm,cortex-a9-global-timer";
677 compatible = "arm,cortex-a9-twd-timer";
685 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
689 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
693 compatible = "amlogic,meson8-rtc";
698 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
700 clock-names = "clkin", "core";
701 amlogic,hhi-sysctrl = <&hhi>;
702 nvmem-cells = <&temperature_calib>;
703 nvmem-cell-names = "temperature_calib";
707 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
713 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
717 secbus2: system-controller@4000 {
718 compatible = "amlogic,meson8-secbus2", "syscon";
724 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
726 clock-names = "core", "clkin";
735 clock-names = "xtal", "pclk";
739 compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
741 clock-names = "xtal", "pclk", "baud";
745 compatible = "amlogic,meson8-uart";
747 clock-names = "xtal", "pclk", "baud";
751 compatible = "amlogic,meson8-uart";
753 clock-names = "xtal", "pclk", "baud";
757 compatible = "amlogic,meson8-uart";
759 clock-names = "xtal", "pclk", "baud";
763 compatible = "amlogic,meson8-usb", "snps,dwc2";
765 clock-names = "otg";
769 compatible = "amlogic,meson8-usb", "snps,dwc2";
771 clock-names = "otg";
775 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
777 clock-names = "usb_general", "usb";
782 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
784 clock-names = "usb_general", "usb";