Lines Matching +full:sck +full:- +full:gpios

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 		stdout-path = "serial0:115200n8";
19 	gpio-restart {
20 		compatible = "gpio-restart";
21 		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
27 	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
31 		pinctrl-0 = <&usart0_pins>;
32 		pinctrl-names = "default";
38 	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
42 		pinctrl-0 = <&fc3_b_pins>;
43 		pinctrl-names = "default";
45 		cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
50 	fc3_b_pins: fc3-b-pins {
51 		/* SCK, MISO, MOSI */
56 	miim_c_pins: miim-c-pins {
62 	sgpio_a_pins: sgpio-a-pins {
63 		/* SCK, D0, D1 */
68 	sgpio_b_pins: sgpio-b-pins {
74 	usart0_pins: usart0-pins {
80 	usbs_a_pins: usbs-a-pins {
88 	pinctrl-0 = <&miim_c_pins>;
89 	pinctrl-names = "default";
90 	reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
91 	clock-frequency = <2500000>;
94 	phy4: ethernet-phy@5 {
96 		coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
99 	phy5: ethernet-phy@6 {
101 		coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
104 	phy6: ethernet-phy@7 {
106 		coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
109 	phy7: ethernet-phy@8 {
111 		coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
129 	phy-handle = <&phy0>;
130 	phy-mode = "gmii";
136 	phy-handle = <&phy1>;
137 	phy-mode = "gmii";
143 	phy-handle = <&phy4>;
144 	phy-mode = "qsgmii";
150 	phy-handle = <&phy5>;
151 	phy-mode = "qsgmii";
157 	phy-handle = <&phy6>;
158 	phy-mode = "qsgmii";
164 	phy-handle = <&phy7>;
165 	phy-mode = "qsgmii";
174 	pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
175 	pinctrl-names = "default";
176 	bus-frequency = <8000000>;
177 	/* arbitrary range because all GPIOs are in software mode */
178 	microchip,sgpio-port-ranges = <0 11>;
195 	pinctrl-0 = <&usbs_a_pins>;
196 	pinctrl-names = "default";
197 	atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>;