Lines Matching +full:0 +full:xb00
10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
54 #clock-cells = <0>;
58 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
60 domain-id = <0>;
64 #clock-cells = <0>;
68 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
74 #clock-cells = <0>;
77 clock-output-names = "hyperlink-0";
78 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
84 #clock-cells = <0>;
88 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
94 #clock-cells = <0>;
98 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
104 #clock-cells = <0>;
108 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
114 #clock-cells = <0>;
118 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
124 #clock-cells = <0>;
128 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
134 #clock-cells = <0>;
138 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
144 #clock-cells = <0>;
148 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
154 #clock-cells = <0>;
158 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
164 #clock-cells = <0>;
168 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
174 #clock-cells = <0>;
178 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
184 #clock-cells = <0>;
188 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
194 #clock-cells = <0>;
197 clock-output-names = "fftc-0";
198 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
204 #clock-cells = <0>;
208 reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
214 #clock-cells = <0>;
218 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
224 #clock-cells = <0>;
228 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
234 #clock-cells = <0>;
238 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
244 #clock-cells = <0>;
248 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
254 #clock-cells = <0>;
258 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
264 #clock-cells = <0>;
267 clock-output-names = "tcp3d-0";
268 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
274 #clock-cells = <0>;
278 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
284 #clock-cells = <0>;
288 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
294 #clock-cells = <0>;
298 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
304 #clock-cells = <0>;
307 clock-output-names = "vcp-0";
308 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
314 #clock-cells = <0>;
318 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
324 #clock-cells = <0>;
328 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
334 #clock-cells = <0>;
338 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
344 #clock-cells = <0>;
348 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
354 #clock-cells = <0>;
358 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
364 #clock-cells = <0>;
368 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
374 #clock-cells = <0>;
378 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
384 #clock-cells = <0>;
388 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
394 #clock-cells = <0>;
398 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
404 #clock-cells = <0>;
408 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
414 #clock-cells = <0>;
418 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;