Lines Matching +full:1 +full:- +full:9 +full:a +full:- +full:d
1 // SPDX-License-Identifier: ISC
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
6 /dts-v1/;
8 #include "intel-ixp43x.dtsi"
13 #address-cells = <1>;
14 #size-cells = <1>;
24 stdout-path = "uart0:115200n8";
32 compatible = "gpio-leds";
33 led-user {
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
46 #address-cells = <1>;
47 #size-cells = <0>;
62 read-only;
65 compatible = "gateworks,pld-gpio";
67 gpio-controller;
68 #gpio-cells = <2>;
72 compatible = "gateworks,pld-gpio";
74 gpio-controller;
75 #gpio-cells = <2>;
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
83 bank-width = <2>;
85 intel,ixp4xx-eb-write-enable = <1>;
93 compatible = "redboot-fis";
95 fis-index-block = <0xff>;
99 compatible = "intel,ixp4xx-compact-flash";
101 * Set up expansion bus config to a really slow timing.
103 * depending on selected PIO mode (0-4).
105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
110 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
112 intel,ixp4xx-eb-mux-address-and-data = <0>;
113 intel,ixp4xx-eb-ahb-split-transfers = <0>;
114 intel,ixp4xx-eb-write-enable = <1>;
115 intel,ixp4xx-eb-byte-access = <1>;
118 interrupt-parent = <&gpio0>;
129 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
132 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map =
137 /* IDSEL 1 */
138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
139 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
140 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
141 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
143 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
144 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
146 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
148 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
151 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
153 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
156 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
158 <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
159 <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
161 <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
163 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
166 <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
171 queue-rx = <&qmgr 4>;
172 queue-txready = <&qmgr 21>;
173 phy-mode = "rgmii";
174 phy-handle = <&phy1>;
177 #address-cells = <1>;
178 #size-cells = <0>;
180 phy1: ethernet-phy@1 {
181 reg = <1>;
184 phy2: ethernet-phy@2 {
192 queue-rx = <&qmgr 2>;
193 queue-txready = <&qmgr 19>;
194 phy-mode = "rgmii";
195 phy-handle = <&phy2>;
196 intel,npe-handle = <&npe 0>;