Lines Matching +full:0 +full:x62000000
17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
61 #clock-cells = <0>;
66 pclk: pclk@0 {
67 #clock-cells = <0>;
76 #clock-cells = <0>;
85 #clock-cells = <0>;
93 reg = <0x08 0x04>;
94 #clock-cells = <0>;
95 lock-offset = <0x14>;
96 vco-offset = <0x08>;
103 reg = <0x1c 0x04>;
104 #clock-cells = <0>;
105 lock-offset = <0x14>;
106 vco-offset = <0x1c>;
113 reg = <0x11000000 0x100>;
114 ranges = <0x0 0x11000000 0x100>;
124 reg = <0x04 0x04>;
125 #clock-cells = <0>;
126 lock-offset = <0x1c>;
127 vco-offset = <0x04>;
134 reg = <0x04 0x04>;
135 #clock-cells = <0>;
136 lock-offset = <0x1c>;
137 vco-offset = <0x04>;
158 valid-mask = <0x003fffff>;
168 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
172 bus-range = <0x00 0xff>;
173 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
174 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
175 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
176 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
177 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
178 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
179 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
180 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
181 0x02000000 0 0x80000000 /* Core module alias memory */
182 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
183 interrupt-map-mask = <0xf800 0 0 0x7>;
186 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
187 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
188 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
189 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
191 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
192 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
193 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
194 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
196 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
197 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
198 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
199 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
201 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
202 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
203 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
204 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
216 arm,primecell-periphid = <0x00041030>;
223 arm,primecell-periphid = <0x00041010>;
230 arm,primecell-periphid = <0x00041010>;
237 arm,primecell-periphid = <0x00041050>;
244 arm,primecell-periphid = <0x00041050>;
252 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
259 ranges = <0xc0000000 0xc0000000 0x40000000>;
264 ranges = <0x00000000 0xc0000000 0x10000000>;
265 dma-ranges = <0x00000000 0xc0000000 0x10000000>;
266 reg = <0xc0000000 0x10000000>;
272 ranges = <0x00000000 0xd0000000 0x10000000>;
273 dma-ranges = <0x00000000 0xd0000000 0x10000000>;
274 reg = <0xd0000000 0x10000000>;
280 ranges = <0x00000000 0xe0000000 0x10000000>;
281 dma-ranges = <0x00000000 0xe0000000 0x10000000>;
282 reg = <0xe0000000 0x10000000>;
288 ranges = <0x00000000 0xf0000000 0x10000000>;
289 dma-ranges = <0x00000000 0xf0000000 0x10000000>;
290 reg = <0xf0000000 0x10000000>;