Lines Matching full:assigned
217 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
219 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
220 assigned-clock-rates = <0>, <100000000>;
244 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
246 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
247 assigned-clock-rates = <0>, <100000000>;
388 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
391 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
392 assigned-clock-rates = <0>, <884736000>, <12288000>;
424 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
427 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
428 assigned-clock-rates = <0>, <884736000>, <36864000>;
435 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
438 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
439 assigned-clock-rates = <0>, <884736000>, <36864000>;
450 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
451 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
458 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
459 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
503 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
504 assigned-clock-rates = <400000000>;