Lines Matching +full:0 +full:x71
22 pinctrl-0 = <&pinctrl_enet2>;
33 #size-cells = <0>;
35 ethphy2_0: ethernet-phy@0 {
37 reg = <0>;
48 pinctrl-0 = <&pinctrl_hog_mba7_1>;
52 MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
53 MX7D_PAD_SD2_WP__ENET2_MDC 0x00
54 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
55 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
56 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
57 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
58 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
59 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
60 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
61 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
62 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
63 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
64 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
65 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
67 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
69 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
76 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
78 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
80 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
88 MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
89 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
96 pinctrl-0 = <&pinctrl_pcie>;
106 pinctrl-0 = <&pinctrl_usbotg2>;