Lines Matching +full:imx21 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
61 #size-cells = <0>;
64 compatible = "arm,cortex-a9";
67 next-level-cache = <&L2>;
68 operating-points = <
75 fsl,soc-operating-points = <
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
91 arm-supply = <®_arm>;
92 soc-supply = <®_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
141 compatible = "fsl,imx6sx-mqs";
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
165 compatible = "mmio-sram";
168 #address-cells = <1>;
169 #size-cells = <1>;
174 compatible = "mmio-sram";
177 #address-cells = <1>;
178 #size-cells = <1>;
182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
188 interrupt-parent = <&intc>;
191 L2: cache-controller@a02000 {
192 compatible = "arm,pl310-cache";
195 cache-unified;
196 cache-level = <2>;
197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 2 3>;
208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_pu>;
212 dma_apbh: dma-apbh@1804000 {
213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
219 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
220 #dma-cells = <1>;
221 dma-channels = <4>;
225 gpmi: nand-controller@1806000{
226 compatible = "fsl,imx6sx-gpmi-nand";
227 #address-cells = <1>;
228 #size-cells = <1>;
230 reg-names = "gpmi-nand", "bch";
232 interrupt-names = "bch";
238 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
241 dma-names = "rx-tx";
246 compatible = "fsl,aips-bus", "simple-bus";
247 #address-cells = <1>;
248 #size-cells = <1>;
252 spba-bus@2000000 {
253 compatible = "fsl,spba-bus", "simple-bus";
254 #address-cells = <1>;
255 #size-cells = <1>;
260 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
265 dma-names = "rx", "tx";
273 clock-names = "core", "rxtx0",
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
289 clock-names = "ipg", "per";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
301 clock-names = "ipg", "per";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
313 clock-names = "ipg", "per";
318 #address-cells = <1>;
319 #size-cells = <0>;
320 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
325 clock-names = "ipg", "per";
330 compatible = "fsl,imx6sx-uart",
331 "fsl,imx6q-uart", "fsl,imx21-uart";
336 clock-names = "ipg", "per";
338 dma-names = "rx", "tx";
343 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
351 clock-names = "core", "mem", "extal",
355 dma-names = "rx", "tx";
360 #sound-dai-cells = <0>;
361 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
366 clock-names = "ipg", "baud";
368 dma-names = "rx", "tx";
369 fsl,fifo-depth = <15>;
374 #sound-dai-cells = <0>;
375 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
380 clock-names = "ipg", "baud";
382 dma-names = "rx", "tx";
383 fsl,fifo-depth = <15>;
388 #sound-dai-cells = <0>;
389 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
394 clock-names = "ipg", "baud";
396 dma-names = "rx", "tx";
397 fsl,fifo-depth = <15>;
402 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
412 clock-names = "mem", "ipg", "asrck_0",
420 dma-names = "rxa", "rxb", "rxc",
422 fsl,asrc-rate = <48000>;
423 fsl,asrc-width = <16>;
429 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
434 clock-names = "ipg", "per";
435 #pwm-cells = <3>;
439 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
444 clock-names = "ipg", "per";
445 #pwm-cells = <3>;
449 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
454 clock-names = "ipg", "per";
455 #pwm-cells = <3>;
459 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
464 clock-names = "ipg", "per";
465 #pwm-cells = <3>;
469 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
474 clock-names = "ipg", "per";
475 fsl,stop-mode = <&gpr 0x10 1>;
480 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
485 clock-names = "ipg", "per";
486 fsl,stop-mode = <&gpr 0x10 2>;
491 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
496 clock-names = "ipg", "per";
500 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
504 gpio-controller;
505 #gpio-cells = <2>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 gpio-ranges = <&iomuxc 0 5 26>;
512 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 gpio-ranges = <&iomuxc 0 31 20>;
524 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
528 gpio-controller;
529 #gpio-cells = <2>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
532 gpio-ranges = <&iomuxc 0 51 29>;
536 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
540 gpio-controller;
541 #gpio-cells = <2>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 gpio-ranges = <&iomuxc 0 80 32>;
548 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
552 gpio-controller;
553 #gpio-cells = <2>;
554 interrupt-controller;
555 #interrupt-cells = <2>;
556 gpio-ranges = <&iomuxc 0 112 24>;
560 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
564 gpio-controller;
565 #gpio-cells = <2>;
566 interrupt-controller;
567 #interrupt-cells = <2>;
568 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
572 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
576 gpio-controller;
577 #gpio-cells = <2>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
584 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
592 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
599 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
606 clks: clock-controller@20c4000 {
607 compatible = "fsl,imx6sx-ccm";
611 #clock-cells = <1>;
613 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
617 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
618 "syscon", "simple-mfd";
624 reg_vdd1p1: regulator-1p1 {
625 compatible = "fsl,anatop-regulator";
626 regulator-name = "vdd1p1";
627 regulator-min-microvolt = <1000000>;
628 regulator-max-microvolt = <1200000>;
629 regulator-always-on;
630 anatop-reg-offset = <0x110>;
631 anatop-vol-bit-shift = <8>;
632 anatop-vol-bit-width = <5>;
633 anatop-min-bit-val = <4>;
634 anatop-min-voltage = <800000>;
635 anatop-max-voltage = <1375000>;
636 anatop-enable-bit = <0>;
639 reg_vdd3p0: regulator-3p0 {
640 compatible = "fsl,anatop-regulator";
641 regulator-name = "vdd3p0";
642 regulator-min-microvolt = <2800000>;
643 regulator-max-microvolt = <3150000>;
644 regulator-always-on;
645 anatop-reg-offset = <0x120>;
646 anatop-vol-bit-shift = <8>;
647 anatop-vol-bit-width = <5>;
648 anatop-min-bit-val = <0>;
649 anatop-min-voltage = <2625000>;
650 anatop-max-voltage = <3400000>;
651 anatop-enable-bit = <0>;
654 reg_vdd2p5: regulator-2p5 {
655 compatible = "fsl,anatop-regulator";
656 regulator-name = "vdd2p5";
657 regulator-min-microvolt = <2250000>;
658 regulator-max-microvolt = <2750000>;
659 regulator-always-on;
660 anatop-reg-offset = <0x130>;
661 anatop-vol-bit-shift = <8>;
662 anatop-vol-bit-width = <5>;
663 anatop-min-bit-val = <0>;
664 anatop-min-voltage = <2100000>;
665 anatop-max-voltage = <2875000>;
666 anatop-enable-bit = <0>;
669 reg_arm: regulator-vddcore {
670 compatible = "fsl,anatop-regulator";
671 regulator-name = "vddarm";
672 regulator-min-microvolt = <725000>;
673 regulator-max-microvolt = <1450000>;
674 regulator-always-on;
675 anatop-reg-offset = <0x140>;
676 anatop-vol-bit-shift = <0>;
677 anatop-vol-bit-width = <5>;
678 anatop-delay-reg-offset = <0x170>;
679 anatop-delay-bit-shift = <24>;
680 anatop-delay-bit-width = <2>;
681 anatop-min-bit-val = <1>;
682 anatop-min-voltage = <725000>;
683 anatop-max-voltage = <1450000>;
686 reg_pcie: regulator-vddpcie {
687 compatible = "fsl,anatop-regulator";
688 regulator-name = "vddpcie";
689 regulator-min-microvolt = <725000>;
690 regulator-max-microvolt = <1450000>;
691 anatop-reg-offset = <0x140>;
692 anatop-vol-bit-shift = <9>;
693 anatop-vol-bit-width = <5>;
694 anatop-delay-reg-offset = <0x170>;
695 anatop-delay-bit-shift = <26>;
696 anatop-delay-bit-width = <2>;
697 anatop-min-bit-val = <1>;
698 anatop-min-voltage = <725000>;
699 anatop-max-voltage = <1450000>;
702 reg_soc: regulator-vddsoc {
703 compatible = "fsl,anatop-regulator";
704 regulator-name = "vddsoc";
705 regulator-min-microvolt = <725000>;
706 regulator-max-microvolt = <1450000>;
707 regulator-always-on;
708 anatop-reg-offset = <0x140>;
709 anatop-vol-bit-shift = <18>;
710 anatop-vol-bit-width = <5>;
711 anatop-delay-reg-offset = <0x170>;
712 anatop-delay-bit-shift = <28>;
713 anatop-delay-bit-width = <2>;
714 anatop-min-bit-val = <1>;
715 anatop-min-voltage = <725000>;
716 anatop-max-voltage = <1450000>;
720 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
721 interrupt-parent = <&gpc>;
724 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
725 nvmem-cell-names = "calib", "temp_grade";
731 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
739 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
747 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
750 snvs_rtc: snvs-rtc-lp {
751 compatible = "fsl,sec-v4.0-mon-rtc-lp";
757 snvs_poweroff: snvs-poweroff {
758 compatible = "syscon-poweroff";
766 snvs_pwrkey: snvs-powerkey {
767 compatible = "fsl,sec-v4.0-pwrkey";
771 wakeup-source;
786 src: reset-controller@20d8000 {
787 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
791 #reset-cells = <1>;
795 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
797 interrupt-controller;
798 #interrupt-cells = <3>;
800 interrupt-parent = <&intc>;
802 clock-names = "ipg";
805 #address-cells = <1>;
806 #size-cells = <0>;
808 power-domain@0 {
810 #power-domain-cells = <0>;
813 pd_pu: power-domain@1 {
815 #power-domain-cells = <0>;
816 power-supply = <®_soc>;
820 pd_disp: power-domain@2 {
822 #power-domain-cells = <0>;
832 pd_pci: power-domain@3 {
834 #power-domain-cells = <0>;
835 power-supply = <®_pcie>;
841 compatible = "fsl,imx6sx-iomuxc";
845 gpr: iomuxc-gpr@20e4000 {
846 compatible = "fsl,imx6sx-iomuxc-gpr",
847 "fsl,imx6q-iomuxc-gpr", "syscon";
851 sdma: dma-controller@20ec000 {
852 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
857 clock-names = "ipg", "ahb";
858 #dma-cells = <3>;
860 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
865 compatible = "fsl,aips-bus", "simple-bus";
866 #address-cells = <1>;
867 #size-cells = <1>;
872 compatible = "fsl,sec-v4.0";
873 #address-cells = <1>;
874 #size-cells = <1>;
877 interrupt-parent = <&intc>;
882 clock-names = "mem", "aclk", "ipg", "emi_slow";
885 compatible = "fsl,sec-v4.0-job-ring";
891 compatible = "fsl,sec-v4.0-job-ring";
898 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
905 ahb-burst-config = <0x0>;
906 tx-burst-size-dword = <0x10>;
907 rx-burst-size-dword = <0x10>;
912 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
918 ahb-burst-config = <0x0>;
919 tx-burst-size-dword = <0x10>;
920 rx-burst-size-dword = <0x10>;
925 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
934 ahb-burst-config = <0x0>;
935 tx-burst-size-dword = <0x10>;
936 rx-burst-size-dword = <0x10>;
941 #index-cells = <1>;
942 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
948 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
950 interrupt-names = "int0", "pps";
958 clock-names = "ipg", "ahb", "ptp",
960 fsl,num-tx-queues = <3>;
961 fsl,num-rx-queues = <3>;
962 fsl,stop-mode = <&gpr 0x10 3>;
976 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
982 clock-names = "ipg", "ahb", "per";
983 bus-width = <4>;
988 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
994 clock-names = "ipg", "ahb", "per";
995 bus-width = <4>;
1000 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1006 clock-names = "ipg", "ahb", "per";
1007 bus-width = <4>;
1012 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1018 clock-names = "ipg", "ahb", "per";
1019 bus-width = <4>;
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1053 memory-controller@21b0000 {
1054 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1060 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1062 interrupt-names = "int0", "pps";
1070 clock-names = "ipg", "ahb", "ptp",
1072 fsl,stop-mode = <&gpr 0x10 4>;
1077 #address-cells = <2>;
1078 #size-cells = <1>;
1079 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1083 fsl,weim-cs-gpr = <&gpr>;
1088 #address-cells = <1>;
1089 #size-cells = <1>;
1090 compatible = "fsl,imx6sx-ocotp", "syscon";
1094 cpu_speed_grade: speed-grade@10 {
1102 tempmon_temp_grade: temp-grade@20 {
1108 compatible = "fsl,imx6sx-sai";
1114 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1115 dma-names = "rx", "tx";
1121 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1127 compatible = "fsl,imx6sx-sai";
1133 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1134 dma-names = "rx", "tx";
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1142 compatible = "fsl,imx6sx-qspi";
1144 reg-names = "QuadSPI", "QuadSPI-memory";
1148 clock-names = "qspi_en", "qspi";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 compatible = "fsl,imx6sx-qspi";
1157 reg-names = "QuadSPI", "QuadSPI-memory";
1161 clock-names = "qspi_en", "qspi";
1166 compatible = "fsl,imx6sx-uart",
1167 "fsl,imx6q-uart", "fsl,imx21-uart";
1172 clock-names = "ipg", "per";
1174 dma-names = "rx", "tx";
1179 compatible = "fsl,imx6sx-uart",
1180 "fsl,imx6q-uart", "fsl,imx21-uart";
1185 clock-names = "ipg", "per";
1187 dma-names = "rx", "tx";
1192 compatible = "fsl,imx6sx-uart",
1193 "fsl,imx6q-uart", "fsl,imx21-uart";
1198 clock-names = "ipg", "per";
1200 dma-names = "rx", "tx";
1205 compatible = "fsl,imx6sx-uart",
1206 "fsl,imx6q-uart", "fsl,imx21-uart";
1211 clock-names = "ipg", "per";
1213 dma-names = "rx", "tx";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1229 compatible = "fsl,aips-bus", "simple-bus";
1230 #address-cells = <1>;
1231 #size-cells = <1>;
1235 spba-bus@2240000 {
1236 compatible = "fsl,spba-bus", "simple-bus";
1237 #address-cells = <1>;
1238 #size-cells = <1>;
1248 clock-names = "disp-axi", "csi_mclk", "dcic";
1253 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1257 clock-names = "axi";
1258 power-domains = <&pd_disp>;
1268 clock-names = "disp-axi", "csi_mclk", "dcic";
1273 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1279 clock-names = "pix", "axi", "disp_axi";
1280 power-domains = <&pd_disp>;
1285 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1291 clock-names = "pix", "axi", "disp_axi";
1292 power-domains = <&pd_disp>;
1298 reg-names = "vadc-vafe", "vadc-vdec";
1301 clock-names = "vadc", "csi";
1302 power-domains = <&pd_disp>;
1308 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1312 clock-names = "adc";
1313 fsl,adck-max-frequency = <30000000>, <40000000>,
1319 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1323 clock-names = "adc";
1324 fsl,adck-max-frequency = <30000000>, <40000000>,
1330 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1345 clock-names = "ipg", "per";
1350 compatible = "fsl,imx6sx-uart",
1351 "fsl,imx6q-uart", "fsl,imx21-uart";
1356 clock-names = "ipg", "per";
1358 dma-names = "rx", "tx";
1363 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1368 clock-names = "ipg", "per";
1369 #pwm-cells = <3>;
1373 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1378 clock-names = "ipg", "per";
1379 #pwm-cells = <3>;
1383 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1388 clock-names = "ipg", "per";
1389 #pwm-cells = <3>;
1393 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1398 clock-names = "ipg", "per";
1399 #pwm-cells = <3>;
1404 compatible = "fsl,imx6sx-pcie";
1406 reg-names = "dbi", "config";
1407 #address-cells = <3>;
1408 #size-cells = <2>;
1410 bus-range = <0x00 0xff>;
1412 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1413 num-lanes = <1>;
1415 interrupt-names = "msi";
1416 #interrupt-cells = <1>;
1417 interrupt-map-mask = <0 0 0 0x7>;
1418 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1426 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1427 power-domains = <&pd_disp>, <&pd_pci>;
1428 power-domain-names = "pcie", "pcie_phy";