Lines Matching +full:0 +full:x4000
61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
135 #clock-cells = <0>;
136 clock-frequency = <0>;
154 #phy-cells = <0>;
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
193 reg = <0x00a02000 0x1000>;
203 reg = <0x01800000 0x4000>;
214 reg = <0x01804000 0x2000>;
229 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
240 dmas = <&dma_apbh 0>;
249 reg = <0x02000000 0x100000>;
256 reg = <0x02000000 0x40000>;
261 reg = <0x02004000 0x4000>;
263 dmas = <&sdma 14 18 0>,
264 <&sdma 15 18 0>;
269 <&clks 0>, <&clks 0>, <&clks 0>,
271 <&clks 0>, <&clks 0>,
283 #size-cells = <0>;
285 reg = <0x02008000 0x4000>;
295 #size-cells = <0>;
297 reg = <0x0200c000 0x4000>;
307 #size-cells = <0>;
309 reg = <0x02010000 0x4000>;
319 #size-cells = <0>;
321 reg = <0x02014000 0x4000>;
332 reg = <0x02020000 0x4000>;
337 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
344 reg = <0x02024000 0x4000>;
353 dmas = <&sdma 23 21 0>,
354 <&sdma 24 21 0>;
360 #sound-dai-cells = <0>;
362 reg = <0x02028000 0x4000>;
367 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
374 #sound-dai-cells = <0>;
376 reg = <0x0202c000 0x4000>;
381 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
388 #sound-dai-cells = <0>;
390 reg = <0x02030000 0x4000>;
395 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
403 reg = <0x02034000 0x4000>;
406 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
409 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
410 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
430 reg = <0x02080000 0x4000>;
440 reg = <0x02084000 0x4000>;
450 reg = <0x02088000 0x4000>;
460 reg = <0x0208c000 0x4000>;
470 reg = <0x02090000 0x4000>;
475 fsl,stop-mode = <&gpr 0x10 1>;
481 reg = <0x02094000 0x4000>;
486 fsl,stop-mode = <&gpr 0x10 2>;
492 reg = <0x02098000 0x4000>;
501 reg = <0x0209c000 0x4000>;
508 gpio-ranges = <&iomuxc 0 5 26>;
513 reg = <0x020a0000 0x4000>;
520 gpio-ranges = <&iomuxc 0 31 20>;
525 reg = <0x020a4000 0x4000>;
532 gpio-ranges = <&iomuxc 0 51 29>;
537 reg = <0x020a8000 0x4000>;
544 gpio-ranges = <&iomuxc 0 80 32>;
549 reg = <0x020ac000 0x4000>;
556 gpio-ranges = <&iomuxc 0 112 24>;
561 reg = <0x020b0000 0x4000>;
568 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
573 reg = <0x020b4000 0x4000>;
580 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
585 reg = <0x020b8000 0x4000>;
593 reg = <0x020bc000 0x4000>;
600 reg = <0x020c0000 0x4000>;
608 reg = <0x020c4000 0x4000>;
619 reg = <0x020c8000 0x1000>;
630 anatop-reg-offset = <0x110>;
636 anatop-enable-bit = <0>;
645 anatop-reg-offset = <0x120>;
648 anatop-min-bit-val = <0>;
651 anatop-enable-bit = <0>;
660 anatop-reg-offset = <0x130>;
663 anatop-min-bit-val = <0>;
666 anatop-enable-bit = <0>;
675 anatop-reg-offset = <0x140>;
676 anatop-vol-bit-shift = <0>;
678 anatop-delay-reg-offset = <0x170>;
691 anatop-reg-offset = <0x140>;
694 anatop-delay-reg-offset = <0x170>;
708 anatop-reg-offset = <0x140>;
711 anatop-delay-reg-offset = <0x170>;
732 reg = <0x020c9000 0x1000>;
740 reg = <0x020ca000 0x1000>;
747 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
748 reg = <0x020cc000 0x4000>;
751 compatible = "fsl,sec-v4.0-mon-rtc-lp";
753 offset = <0x34>;
760 offset = <0x38>;
761 value = <0x60>;
762 mask = <0x60>;
767 compatible = "fsl,sec-v4.0-pwrkey";
777 reg = <0x020d0000 0x4000>;
782 reg = <0x020d4000 0x4000>;
788 reg = <0x020d8000 0x4000>;
796 reg = <0x020dc000 0x4000>;
806 #size-cells = <0>;
808 power-domain@0 {
809 reg = <0>;
810 #power-domain-cells = <0>;
815 #power-domain-cells = <0>;
822 #power-domain-cells = <0>;
834 #power-domain-cells = <0>;
842 reg = <0x020e0000 0x4000>;
848 reg = <0x020e4000 0x4000>;
853 reg = <0x020ec000 0x4000>;
868 reg = <0x02100000 0x100000>;
872 compatible = "fsl,sec-v4.0";
875 reg = <0x2100000 0x10000>;
876 ranges = <0 0x2100000 0x10000>;
885 compatible = "fsl,sec-v4.0-job-ring";
886 reg = <0x1000 0x1000>;
891 compatible = "fsl,sec-v4.0-job-ring";
892 reg = <0x2000 0x1000>;
899 reg = <0x02184000 0x200>;
903 fsl,usbmisc = <&usbmisc 0>;
905 ahb-burst-config = <0x0>;
906 tx-burst-size-dword = <0x10>;
907 rx-burst-size-dword = <0x10>;
913 reg = <0x02184200 0x200>;
918 ahb-burst-config = <0x0>;
919 tx-burst-size-dword = <0x10>;
920 rx-burst-size-dword = <0x10>;
926 reg = <0x02184400 0x200>;
934 ahb-burst-config = <0x0>;
935 tx-burst-size-dword = <0x10>;
936 rx-burst-size-dword = <0x10>;
943 reg = <0x02184800 0x200>;
949 reg = <0x02188000 0x4000>;
962 fsl,stop-mode = <&gpr 0x10 3>;
967 reg = <0x0218c000 0x4000>;
977 reg = <0x02190000 0x4000>;
989 reg = <0x02194000 0x4000>;
1001 reg = <0x02198000 0x4000>;
1013 reg = <0x0219c000 0x4000>;
1025 #size-cells = <0>;
1027 reg = <0x021a0000 0x4000>;
1035 #size-cells = <0>;
1037 reg = <0x021a4000 0x4000>;
1045 #size-cells = <0>;
1047 reg = <0x021a8000 0x4000>;
1055 reg = <0x021b0000 0x4000>;
1061 reg = <0x021b4000 0x4000>;
1072 fsl,stop-mode = <&gpr 0x10 4>;
1080 reg = <0x021b8000 0x4000>;
1091 reg = <0x021bc000 0x4000>;
1095 reg = <0x10 4>;
1099 reg = <0x38 4>;
1103 reg = <0x20 4>;
1109 reg = <0x021d4000 0x4000>;
1113 <&clks 0>, <&clks 0>;
1116 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1122 reg = <0x021d8000 0x4000>;
1128 reg = <0x021dc000 0x4000>;
1132 <&clks 0>, <&clks 0>;
1135 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1141 #size-cells = <0>;
1143 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1154 #size-cells = <0>;
1156 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1168 reg = <0x021e8000 0x4000>;
1173 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1181 reg = <0x021ec000 0x4000>;
1186 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1194 reg = <0x021f0000 0x4000>;
1199 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1207 reg = <0x021f4000 0x4000>;
1212 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1219 #size-cells = <0>;
1221 reg = <0x021f8000 0x4000>;
1232 reg = <0x02200000 0x100000>;
1239 reg = <0x02240000 0x40000>;
1243 reg = <0x02214000 0x4000>;
1254 reg = <0x02218000 0x4000>;
1263 reg = <0x0221c000 0x4000>;
1274 reg = <0x02220000 0x4000>;
1286 reg = <0x02224000 0x4000>;
1297 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1309 reg = <0x02280000 0x4000>;
1320 reg = <0x02284000 0x4000>;
1331 reg = <0x02288000 0x4000>;
1339 #size-cells = <0>;
1341 reg = <0x0228c000 0x4000>;
1352 reg = <0x022a0000 0x4000>;
1357 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1364 reg = <0x022a4000 0x4000>;
1374 reg = <0x022a8000 0x4000>;
1384 reg = <0x022ac000 0x4000>;
1394 reg = <0x0022b0000 0x4000>;
1405 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1410 bus-range = <0x00 0xff>;
1411 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1412 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1417 interrupt-map-mask = <0 0 0 0x7>;
1418 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1419 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1420 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1421 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;