Lines Matching +full:imx53 +full:- +full:vpu
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
93 remote-endpoint = <&ipu1_di0_lvds0>;
101 remote-endpoint = <&ipu1_di1_lvds0>;
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
116 remote-endpoint = <&ipu1_di0_lvds1>;
124 remote-endpoint = <&ipu1_di1_lvds1>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
153 dma_apbh: dma-apbh@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 #dma-cells = <1>;
162 dma-channels = <4>;
166 gpmi: nand-controller@112000 {
167 compatible = "fsl,imx6q-gpmi-nand";
169 reg-names = "gpmi-nand", "bch";
171 interrupt-names = "bch";
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
180 dma-names = "rx-tx";
190 clock-names = "iahb", "isfr";
194 #address-cells = <1>;
195 #size-cells = <0>;
201 remote-endpoint = <&ipu1_di0_hdmi>;
209 remote-endpoint = <&ipu1_di1_hdmi>;
222 clock-names = "bus", "core", "shader";
223 power-domains = <&pd_pu>;
224 #cooling-cells = <2>;
233 clock-names = "bus", "core";
234 power-domains = <&pd_pu>;
235 #cooling-cells = <2>;
239 compatible = "arm,cortex-a9-twd-timer";
242 interrupt-parent = <&intc>;
246 intc: interrupt-controller@a01000 {
247 compatible = "arm,cortex-a9-gic";
248 #interrupt-cells = <3>;
249 interrupt-controller;
252 interrupt-parent = <&intc>;
255 L2: cache-controller@a02000 {
256 compatible = "arm,pl310-cache";
259 cache-unified;
260 cache-level = <2>;
261 arm,tag-latency = <4 2 3>;
262 arm,data-latency = <4 2 3>;
263 arm,shared-override;
267 compatible = "fsl,imx6q-pcie";
270 reg-names = "dbi", "config";
271 #address-cells = <3>;
272 #size-cells = <2>;
274 bus-range = <0x00 0xff>;
276 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 num-lanes = <1>;
279 interrupt-names = "msi";
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0x7>;
282 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
289 clock-names = "pcie", "pcie_bus", "pcie_phy";
294 compatible = "fsl,aips-bus", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
300 spba-bus@2000000 {
301 compatible = "fsl,spba-bus", "simple-bus";
302 #address-cells = <1>;
303 #size-cells = <1>;
308 compatible = "fsl,imx35-spdif";
313 dma-names = "rx", "tx";
319 clock-names = "core", "rxtx0",
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
335 clock-names = "ipg", "per";
337 dma-names = "rx", "tx";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
349 clock-names = "ipg", "per";
351 dma-names = "rx", "tx";
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
363 clock-names = "ipg", "per";
365 dma-names = "rx", "tx";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
377 clock-names = "ipg", "per";
379 dma-names = "rx", "tx";
384 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
389 clock-names = "ipg", "per";
391 dma-names = "rx", "tx";
396 #sound-dai-cells = <0>;
397 compatible = "fsl,imx35-esai";
405 clock-names = "core", "mem", "extal", "fsys", "spba";
407 dma-names = "rx", "tx";
412 #sound-dai-cells = <0>;
413 compatible = "fsl,imx6q-ssi",
414 "fsl,imx51-ssi";
419 clock-names = "ipg", "baud";
422 dma-names = "rx", "tx";
423 fsl,fifo-depth = <15>;
428 #sound-dai-cells = <0>;
429 compatible = "fsl,imx6q-ssi",
430 "fsl,imx51-ssi";
435 clock-names = "ipg", "baud";
438 dma-names = "rx", "tx";
439 fsl,fifo-depth = <15>;
444 #sound-dai-cells = <0>;
445 compatible = "fsl,imx6q-ssi",
446 "fsl,imx51-ssi";
451 clock-names = "ipg", "baud";
454 dma-names = "rx", "tx";
455 fsl,fifo-depth = <15>;
460 compatible = "fsl,imx53-asrc";
470 clock-names = "mem", "ipg", "asrck_0",
477 dma-names = "rxa", "rxb", "rxc",
479 fsl,asrc-rate = <48000>;
480 fsl,asrc-width = <16>;
484 spba-bus@203c000 {
489 vpu: vpu@2040000 { label
494 interrupt-names = "bit", "jpeg";
497 clock-names = "per", "ahb";
498 power-domains = <&pd_pu>;
508 #pwm-cells = <3>;
509 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
514 clock-names = "ipg", "per";
519 #pwm-cells = <3>;
520 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
525 clock-names = "ipg", "per";
530 #pwm-cells = <3>;
531 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
536 clock-names = "ipg", "per";
541 #pwm-cells = <3>;
542 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
547 clock-names = "ipg", "per";
552 compatible = "fsl,imx6q-flexcan";
557 clock-names = "ipg", "per";
558 fsl,stop-mode = <&gpr 0x34 28>;
563 compatible = "fsl,imx6q-flexcan";
568 clock-names = "ipg", "per";
569 fsl,stop-mode = <&gpr 0x34 29>;
574 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
580 clock-names = "ipg", "per", "osc_per";
584 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
595 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
599 gpio-controller;
600 #gpio-cells = <2>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
606 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
610 gpio-controller;
611 #gpio-cells = <2>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
617 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
621 gpio-controller;
622 #gpio-cells = <2>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
628 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
632 gpio-controller;
633 #gpio-cells = <2>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
639 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
643 gpio-controller;
644 #gpio-cells = <2>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
650 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
654 gpio-controller;
655 #gpio-cells = <2>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
661 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
676 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
683 clks: clock-controller@20c4000 {
684 compatible = "fsl,imx6q-ccm";
688 #clock-cells = <1>;
692 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
698 reg_vdd1p1: regulator-1p1 {
699 compatible = "fsl,anatop-regulator";
700 regulator-name = "vdd1p1";
701 regulator-min-microvolt = <1000000>;
702 regulator-max-microvolt = <1200000>;
703 regulator-always-on;
704 anatop-reg-offset = <0x110>;
705 anatop-vol-bit-shift = <8>;
706 anatop-vol-bit-width = <5>;
707 anatop-min-bit-val = <4>;
708 anatop-min-voltage = <800000>;
709 anatop-max-voltage = <1375000>;
710 anatop-enable-bit = <0>;
713 reg_vdd3p0: regulator-3p0 {
714 compatible = "fsl,anatop-regulator";
715 regulator-name = "vdd3p0";
716 regulator-min-microvolt = <2800000>;
717 regulator-max-microvolt = <3150000>;
718 regulator-always-on;
719 anatop-reg-offset = <0x120>;
720 anatop-vol-bit-shift = <8>;
721 anatop-vol-bit-width = <5>;
722 anatop-min-bit-val = <0>;
723 anatop-min-voltage = <2625000>;
724 anatop-max-voltage = <3400000>;
725 anatop-enable-bit = <0>;
728 reg_vdd2p5: regulator-2p5 {
729 compatible = "fsl,anatop-regulator";
730 regulator-name = "vdd2p5";
731 regulator-min-microvolt = <2250000>;
732 regulator-max-microvolt = <2750000>;
733 regulator-always-on;
734 anatop-reg-offset = <0x130>;
735 anatop-vol-bit-shift = <8>;
736 anatop-vol-bit-width = <5>;
737 anatop-min-bit-val = <0>;
738 anatop-min-voltage = <2100000>;
739 anatop-max-voltage = <2875000>;
740 anatop-enable-bit = <0>;
743 reg_arm: regulator-vddcore {
744 compatible = "fsl,anatop-regulator";
745 regulator-name = "vddarm";
746 regulator-min-microvolt = <725000>;
747 regulator-max-microvolt = <1450000>;
748 regulator-always-on;
749 anatop-reg-offset = <0x140>;
750 anatop-vol-bit-shift = <0>;
751 anatop-vol-bit-width = <5>;
752 anatop-delay-reg-offset = <0x170>;
753 anatop-delay-bit-shift = <24>;
754 anatop-delay-bit-width = <2>;
755 anatop-min-bit-val = <1>;
756 anatop-min-voltage = <725000>;
757 anatop-max-voltage = <1450000>;
760 reg_pu: regulator-vddpu {
761 compatible = "fsl,anatop-regulator";
762 regulator-name = "vddpu";
763 regulator-min-microvolt = <725000>;
764 regulator-max-microvolt = <1450000>;
765 regulator-enable-ramp-delay = <380>;
766 anatop-reg-offset = <0x140>;
767 anatop-vol-bit-shift = <9>;
768 anatop-vol-bit-width = <5>;
769 anatop-delay-reg-offset = <0x170>;
770 anatop-delay-bit-shift = <26>;
771 anatop-delay-bit-width = <2>;
772 anatop-min-bit-val = <1>;
773 anatop-min-voltage = <725000>;
774 anatop-max-voltage = <1450000>;
777 reg_soc: regulator-vddsoc {
778 compatible = "fsl,anatop-regulator";
779 regulator-name = "vddsoc";
780 regulator-min-microvolt = <725000>;
781 regulator-max-microvolt = <1450000>;
782 regulator-always-on;
783 anatop-reg-offset = <0x140>;
784 anatop-vol-bit-shift = <18>;
785 anatop-vol-bit-width = <5>;
786 anatop-delay-reg-offset = <0x170>;
787 anatop-delay-bit-shift = <28>;
788 anatop-delay-bit-width = <2>;
789 anatop-min-bit-val = <1>;
790 anatop-min-voltage = <725000>;
791 anatop-max-voltage = <1450000>;
795 compatible = "fsl,imx6q-tempmon";
796 interrupt-parent = <&gpc>;
799 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
800 nvmem-cell-names = "calib", "temp_grade";
802 #thermal-sensor-cells = <0>;
807 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
815 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
834 snvs_poweroff: snvs-poweroff {
835 compatible = "syscon-poweroff";
843 snvs_pwrkey: snvs-powerkey {
844 compatible = "fsl,sec-v4.0-pwrkey";
848 wakeup-source;
852 snvs_lpgpr: snvs-lpgpr {
853 compatible = "fsl,imx6q-snvs-lpgpr";
867 src: reset-controller@20d8000 {
868 compatible = "fsl,imx6q-src", "fsl,imx51-src";
872 #reset-cells = <1>;
876 compatible = "fsl,imx6q-gpc";
878 interrupt-controller;
879 #interrupt-cells = <3>;
881 interrupt-parent = <&intc>;
883 clock-names = "ipg";
886 #address-cells = <1>;
887 #size-cells = <0>;
889 power-domain@0 {
891 #power-domain-cells = <0>;
893 pd_pu: power-domain@1 {
895 #power-domain-cells = <0>;
896 power-supply = <®_pu>;
907 gpr: iomuxc-gpr@20e0000 {
908 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
911 mux: mux-controller {
912 compatible = "mmio-mux";
913 #mux-control-cells = <1>;
918 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
932 sdma: dma-controller@20ec000 {
933 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
938 clock-names = "ipg", "ahb";
939 #dma-cells = <3>;
940 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
945 compatible = "fsl,aips-bus", "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <1>;
952 compatible = "fsl,sec-v4.0";
953 #address-cells = <1>;
954 #size-cells = <1>;
961 clock-names = "mem", "aclk", "ipg", "emi_slow";
964 compatible = "fsl,sec-v4.0-job-ring";
970 compatible = "fsl,sec-v4.0-job-ring";
981 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
987 ahb-burst-config = <0x0>;
988 tx-burst-size-dword = <0x10>;
989 rx-burst-size-dword = <0x10>;
994 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1008 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1023 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1031 ahb-burst-config = <0x0>;
1032 tx-burst-size-dword = <0x10>;
1033 rx-burst-size-dword = <0x10>;
1038 #index-cells = <1>;
1039 compatible = "fsl,imx6q-usbmisc";
1045 compatible = "fsl,imx6q-fec";
1047 interrupt-names = "int0", "pps";
1054 clock-names = "ipg", "ahb", "ptp", "enet_out";
1055 fsl,stop-mode = <&gpr 0x34 27>;
1067 compatible = "fsl,imx6q-usdhc";
1073 clock-names = "ipg", "ahb", "per";
1074 bus-width = <4>;
1079 compatible = "fsl,imx6q-usdhc";
1085 clock-names = "ipg", "ahb", "per";
1086 bus-width = <4>;
1091 compatible = "fsl,imx6q-usdhc";
1097 clock-names = "ipg", "ahb", "per";
1098 bus-width = <4>;
1103 compatible = "fsl,imx6q-usdhc";
1109 clock-names = "ipg", "ahb", "per";
1110 bus-width = <4>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1148 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1149 compatible = "fsl,imx6q-mmdc";
1154 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1155 compatible = "fsl,imx6q-mmdc";
1161 #address-cells = <2>;
1162 #size-cells = <1>;
1163 compatible = "fsl,imx6q-weim";
1167 fsl,weim-cs-gpr = <&gpr>;
1172 compatible = "fsl,imx6q-ocotp", "syscon";
1175 #address-cells = <1>;
1176 #size-cells = <1>;
1178 cpu_speed_grade: speed-grade@10 {
1186 tempmon_temp_grade: temp-grade@20 {
1202 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1208 compatible = "fsl,imx6-mipi-csi2";
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1216 clock-names = "dphy", "ref", "pix";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 remote-endpoint = <&ipu1_di0_mipi>;
1240 remote-endpoint = <&ipu1_di1_mipi>;
1247 compatible = "fsl,imx6q-vdoa";
1254 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1259 clock-names = "ipg", "per";
1261 dma-names = "rx", "tx";
1266 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1271 clock-names = "ipg", "per";
1273 dma-names = "rx", "tx";
1278 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1283 clock-names = "ipg", "per";
1285 dma-names = "rx", "tx";
1290 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1295 clock-names = "ipg", "per";
1297 dma-names = "rx", "tx";
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 compatible = "fsl,imx6q-ipu";
1312 clock-names = "bus", "di0", "di1";
1319 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1338 remote-endpoint = <&hdmi_mux_0>;
1343 remote-endpoint = <&mipi_mux_0>;
1348 remote-endpoint = <&lvds0_mux_0>;
1353 remote-endpoint = <&lvds1_mux_0>;
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1368 remote-endpoint = <&hdmi_mux_1>;
1373 remote-endpoint = <&mipi_mux_1>;
1378 remote-endpoint = <&lvds0_mux_1>;
1383 remote-endpoint = <&lvds1_mux_1>;