Lines Matching +full:0 +full:x4000
59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
108 #size-cells = <0>;
112 port@0 {
113 reg = <0>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
138 #phy-cells = <0>;
143 #phy-cells = <0>;
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&dma_apbh 0>;
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
195 #size-cells = <0>;
197 port@0 {
198 reg = <0>;
217 reg = <0x00130000 0x4000>;
218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
229 reg = <0x00134000 0x4000>;
230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
240 reg = <0x00a00600 0x20>;
241 interrupts = <1 13 0xf01>;
250 reg = <0x00a01000 0x1000>,
251 <0x00a00100 0x100>;
257 reg = <0x00a02000 0x1000>;
258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
268 reg = <0x01ffc000 0x04000>,
269 <0x01f00000 0x80000>;
274 bus-range = <0x00 0xff>;
275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */
276 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
281 interrupt-map-mask = <0 0 0 0x7>;
282 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
297 reg = <0x02000000 0x100000>;
304 reg = <0x02000000 0x40000>;
309 reg = <0x02004000 0x4000>;
310 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
311 dmas = <&sdma 14 18 0>,
312 <&sdma 15 18 0>;
329 #size-cells = <0>;
331 reg = <0x02008000 0x4000>;
332 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
343 #size-cells = <0>;
345 reg = <0x0200c000 0x4000>;
346 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
357 #size-cells = <0>;
359 reg = <0x02010000 0x4000>;
360 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
371 #size-cells = <0>;
373 reg = <0x02014000 0x4000>;
374 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
385 reg = <0x02020000 0x4000>;
386 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
390 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
396 #sound-dai-cells = <0>;
398 reg = <0x02024000 0x4000>;
399 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
406 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
412 #sound-dai-cells = <0>;
415 reg = <0x02028000 0x4000>;
416 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
420 dmas = <&sdma 37 1 0>,
421 <&sdma 38 1 0>;
428 #sound-dai-cells = <0>;
431 reg = <0x0202c000 0x4000>;
432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
436 dmas = <&sdma 41 1 0>,
437 <&sdma 42 1 0>;
444 #sound-dai-cells = <0>;
447 reg = <0x02030000 0x4000>;
448 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
452 dmas = <&sdma 45 1 0>,
453 <&sdma 46 1 0>;
461 reg = <0x02034000 0x4000>;
462 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
464 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
468 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
485 reg = <0x0203c000 0x4000>;
491 reg = <0x02040000 0x3c000>;
492 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
493 <0 3 IRQ_TYPE_LEVEL_HIGH>;
504 reg = <0x0207c000 0x4000>;
510 reg = <0x02080000 0x4000>;
511 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
521 reg = <0x02084000 0x4000>;
522 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
532 reg = <0x02088000 0x4000>;
533 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
543 reg = <0x0208c000 0x4000>;
544 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
553 reg = <0x02090000 0x4000>;
554 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
558 fsl,stop-mode = <&gpr 0x34 28>;
564 reg = <0x02094000 0x4000>;
565 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
569 fsl,stop-mode = <&gpr 0x34 29>;
575 reg = <0x02098000 0x4000>;
576 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0x0209c000 0x4000>;
586 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
587 <0 67 IRQ_TYPE_LEVEL_HIGH>;
596 reg = <0x020a0000 0x4000>;
597 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
598 <0 69 IRQ_TYPE_LEVEL_HIGH>;
607 reg = <0x020a4000 0x4000>;
608 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
609 <0 71 IRQ_TYPE_LEVEL_HIGH>;
618 reg = <0x020a8000 0x4000>;
619 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
620 <0 73 IRQ_TYPE_LEVEL_HIGH>;
629 reg = <0x020ac000 0x4000>;
630 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
631 <0 75 IRQ_TYPE_LEVEL_HIGH>;
640 reg = <0x020b0000 0x4000>;
641 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
642 <0 77 IRQ_TYPE_LEVEL_HIGH>;
651 reg = <0x020b4000 0x4000>;
652 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
653 <0 79 IRQ_TYPE_LEVEL_HIGH>;
662 reg = <0x020b8000 0x4000>;
663 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
670 reg = <0x020bc000 0x4000>;
671 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
677 reg = <0x020c0000 0x4000>;
678 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
685 reg = <0x020c4000 0x4000>;
686 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
687 <0 88 IRQ_TYPE_LEVEL_HIGH>;
693 reg = <0x020c8000 0x1000>;
694 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
695 <0 54 IRQ_TYPE_LEVEL_HIGH>,
696 <0 127 IRQ_TYPE_LEVEL_HIGH>;
704 anatop-reg-offset = <0x110>;
710 anatop-enable-bit = <0>;
719 anatop-reg-offset = <0x120>;
722 anatop-min-bit-val = <0>;
725 anatop-enable-bit = <0>;
734 anatop-reg-offset = <0x130>;
737 anatop-min-bit-val = <0>;
740 anatop-enable-bit = <0>;
749 anatop-reg-offset = <0x140>;
750 anatop-vol-bit-shift = <0>;
752 anatop-delay-reg-offset = <0x170>;
766 anatop-reg-offset = <0x140>;
769 anatop-delay-reg-offset = <0x170>;
783 anatop-reg-offset = <0x140>;
786 anatop-delay-reg-offset = <0x170>;
797 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
802 #thermal-sensor-cells = <0>;
808 reg = <0x020c9000 0x1000>;
809 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
816 reg = <0x020ca000 0x1000>;
817 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x020cc000 0x4000>;
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
829 offset = <0x34>;
830 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
831 <0 20 IRQ_TYPE_LEVEL_HIGH>;
837 offset = <0x38>;
838 value = <0x60>;
839 mask = <0x60>;
844 compatible = "fsl,sec-v4.0-pwrkey";
858 reg = <0x020d0000 0x4000>;
859 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
863 reg = <0x020d4000 0x4000>;
864 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
869 reg = <0x020d8000 0x4000>;
870 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
871 <0 96 IRQ_TYPE_LEVEL_HIGH>;
877 reg = <0x020dc000 0x4000>;
880 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
887 #size-cells = <0>;
889 power-domain@0 {
890 reg = <0>;
891 #power-domain-cells = <0>;
895 #power-domain-cells = <0>;
909 reg = <0x20e0000 0x38>;
919 reg = <0x20e0000 0x4000>;
923 reg = <0x020e4000 0x4000>;
924 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
928 reg = <0x020e8000 0x4000>;
929 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
934 reg = <0x020ec000 0x4000>;
935 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
948 reg = <0x02100000 0x100000>;
952 compatible = "fsl,sec-v4.0";
955 reg = <0x2100000 0x10000>;
956 ranges = <0 0x2100000 0x10000>;
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x1000 0x1000>;
970 compatible = "fsl,sec-v4.0-job-ring";
971 reg = <0x2000 0x1000>;
977 reg = <0x0217c000 0x4000>;
982 reg = <0x02184000 0x200>;
983 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
986 fsl,usbmisc = <&usbmisc 0>;
987 ahb-burst-config = <0x0>;
988 tx-burst-size-dword = <0x10>;
989 rx-burst-size-dword = <0x10>;
995 reg = <0x02184200 0x200>;
996 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1009 reg = <0x02184400 0x200>;
1010 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1024 reg = <0x02184600 0x200>;
1025 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1031 ahb-burst-config = <0x0>;
1032 tx-burst-size-dword = <0x10>;
1033 rx-burst-size-dword = <0x10>;
1040 reg = <0x02184800 0x200>;
1046 reg = <0x02188000 0x4000>;
1048 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1049 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1055 fsl,stop-mode = <&gpr 0x34 27>;
1060 reg = <0x0218c000 0x4000>;
1061 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1068 reg = <0x02190000 0x4000>;
1069 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1080 reg = <0x02194000 0x4000>;
1081 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1092 reg = <0x02198000 0x4000>;
1093 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1104 reg = <0x0219c000 0x4000>;
1105 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1116 #size-cells = <0>;
1118 reg = <0x021a0000 0x4000>;
1119 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1126 #size-cells = <0>;
1128 reg = <0x021a4000 0x4000>;
1129 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1136 #size-cells = <0>;
1138 reg = <0x021a8000 0x4000>;
1139 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1145 reg = <0x021ac000 0x4000>;
1150 reg = <0x021b0000 0x4000>;
1156 reg = <0x021b4000 0x4000>;
1164 reg = <0x021b8000 0x4000>;
1165 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1173 reg = <0x021bc000 0x4000>;
1179 reg = <0x10 4>;
1183 reg = <0x38 4>;
1187 reg = <0x20 4>;
1192 reg = <0x021d0000 0x4000>;
1193 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1197 reg = <0x021d4000 0x4000>;
1198 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1203 reg = <0x021d8000 0x4000>;
1209 reg = <0x021dc000 0x4000>;
1211 #size-cells = <0>;
1212 interrupts = <0 100 0x04>, <0 101 0x04>;
1221 reg = <0x021e0000 0x4000>;
1226 #size-cells = <0>;
1228 port@0 {
1229 reg = <0>;
1248 reg = <0x021e4000 0x4000>;
1249 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1255 reg = <0x021e8000 0x4000>;
1256 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1260 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1267 reg = <0x021ec000 0x4000>;
1268 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1272 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1279 reg = <0x021f0000 0x4000>;
1280 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1284 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1291 reg = <0x021f4000 0x4000>;
1292 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1296 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1304 #size-cells = <0>;
1306 reg = <0x02400000 0x400000>;
1307 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1308 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1315 ipu1_csi0: port@0 {
1316 reg = <0>;
1329 #size-cells = <0>;
1332 ipu1_di0_disp0: endpoint@0 {
1333 reg = <0>;
1359 #size-cells = <0>;
1362 ipu1_di1_disp1: endpoint@0 {
1363 reg = <0>;