Lines Matching +full:0 +full:x80000000
14 reg = <0x90000000 0x10000000>; /* 256M */
20 pinctrl-0 = <&pinctrl_fec>;
26 pinctrl-0 = <&pinctrl_i2c1>;
31 reg = <0x51>;
36 gpios = <&gpio4 0 1>;
38 interrupts = <0x0 0x8>;
40 pinctrl-0 = <&pinctrl_tsc2007_1>;
41 reg = <0x49>;
50 MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
51 MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
57 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
58 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
59 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
60 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
61 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
62 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
63 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
64 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
65 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
66 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
67 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
68 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
69 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
70 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
71 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
72 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
73 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
74 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
80 MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
81 MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed