Lines Matching +full:0 +full:x6a000000
23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
201 pinctrl-0 = <&rtc_default_pins>;
206 reg = <0x46000000 0x100>;
219 pinctrl-0 = <&sata_default_pins>;
227 reg = <0x48000000 0x1000>;
235 reg = <0x4b000000 0x100>;
238 pinctrl-0 = <&power_default_pins>;
243 reg = <0x4d000000 0x100>;
255 reg = <0x4e000000 0x100>;
267 reg = <0x4f000000 0x100>;
283 reg = <0x50000000 0x100>;
288 pinctrl-0 = <&pci_default_pins>;
295 interrupt-map-mask = <0xf800 0 0 7>;
297 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
298 <0x4800 0 0 2 &pci_intc 1>,
299 <0x4800 0 0 3 &pci_intc 2>,
300 <0x4800 0 0 4 &pci_intc 3>,
301 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
302 <0x5000 0 0 2 &pci_intc 2>,
303 <0x5000 0 0 3 &pci_intc 3>,
304 <0x5000 0 0 4 &pci_intc 0>,
305 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
306 <0x5800 0 0 2 &pci_intc 3>,
307 <0x5800 0 0 3 &pci_intc 0>,
308 <0x5800 0 0 4 &pci_intc 1>,
309 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
310 <0x6000 0 0 2 &pci_intc 0>,
311 <0x6000 0 0 3 &pci_intc 1>,
312 <0x6000 0 0 4 &pci_intc 2>;
314 bus-range = <0x00 0xff>;
317 /* 1MiB I/O space 0x50000000-0x500fffff */
318 <0x01000000 0 0 0x50000000 0 0x00100000>,
319 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
320 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
324 /* 128MiB at 0x00000000-0x07ffffff */
325 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
326 /* 64MiB at 0x00000000-0x03ffffff */
327 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
328 /* 64MiB at 0x00000000-0x03ffffff */
329 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
339 #address-cells = <0>;
346 reg = <0x60000000 0x4000>, /* Global registers, queue */
347 <0x60004000 0x2000>, /* V-bit */
348 <0x60006000 0x2000>; /* A-bit */
350 pinctrl-0 = <&gmii_default_pins>;
356 gmac0: ethernet-port@0 {
358 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
359 <0x6000a000 0x2000>; /* Port 0 GMAC */
369 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
370 <0x6000e000 0x2000>; /* Port 1 GMAC */
381 reg = <0x62000000 0x10000>;
389 reg = <0x63000000 0x1000>;
397 #size-cells = <0>;
402 reg = <0x63400000 0x1000>;
410 #size-cells = <0>;
416 arm,primecell-periphid = <0x0003b080>;
417 reg = <0x67000000 0x1000>;
432 reg = <0x6a000000 0x1000>;
439 pinctrl-0 = <&tvc_default_pins>;
445 reg = <0x68000000 0x1000>;
459 pinctrl-0 = <&usb_default_pins>;
466 reg = <0x69000000 0x1000>;