Lines Matching +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
45 cluster_a15_opp_table: opp-table0 {
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
52 clock-latency-ns = <140000>;
54 opp-1700000000 {
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500 1212500 1500000>;
57 clock-latency-ns = <140000>;
59 opp-1600000000 {
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000 1175000 1500000>;
62 clock-latency-ns = <140000>;
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500 1137500 1500000>;
67 clock-latency-ns = <140000>;
69 opp-1400000000 {
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500 1112500 1500000>;
72 clock-latency-ns = <140000>;
74 opp-1300000000 {
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500 1062500 1500000>;
77 clock-latency-ns = <140000>;
79 opp-1200000000 {
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500 1037500 1500000>;
82 clock-latency-ns = <140000>;
84 opp-1100000000 {
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500 1012500 1500000>;
87 clock-latency-ns = <140000>;
89 opp-1000000000 {
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500 987500 1500000>;
92 clock-latency-ns = <140000>;
94 opp-900000000 {
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500 962500 1500000>;
97 clock-latency-ns = <140000>;
99 opp-800000000 {
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500 937500 1500000>;
102 clock-latency-ns = <140000>;
104 opp-700000000 {
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500 912500 1500000>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp-table1 {
112 compatible = "operating-points-v2";
113 opp-shared;
115 opp-1300000000 {
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
120 opp-1200000000 {
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
125 opp-1100000000 {
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
130 opp-1000000000 {
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
135 opp-900000000 {
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
140 opp-800000000 {
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
145 opp-700000000 {
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
150 opp-600000000 {
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
161 #size-cells = <1>;
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
177 clock: clock-controller@10010000 { label
178 compatible = "samsung,exynos5420-clock", "syscon";
180 #clock-cells = <1>;
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
186 #clock-cells = <1>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
194 compatible = "samsung,mfc-v7";
197 clocks = <&clock CLK_MFC>;
198 clock-names = "mfc";
199 power-domains = <&mfc_pd>;
201 iommu-names = "left", "right";
205 compatible = "samsung,exynos5420-dw-mshc-smu";
207 #address-cells = <1>;
208 #size-cells = <0>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
212 fifo-depth = <0x40>;
217 compatible = "samsung,exynos5420-dw-mshc-smu";
219 #address-cells = <1>;
220 #size-cells = <0>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x40>;
229 compatible = "samsung,exynos5420-dw-mshc";
231 #address-cells = <1>;
232 #size-cells = <0>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
240 dmc: memory-controller@10c20000 {
241 compatible = "samsung,exynos5422-dmc";
243 clocks = <&clock CLK_FOUT_SPLL>,
244 <&clock CLK_MOUT_SCLK_SPLL>,
245 <&clock CLK_FF_DOUT_SPLL2>,
246 <&clock CLK_FOUT_BPLL>,
247 <&clock CLK_MOUT_BPLL>,
248 <&clock CLK_SCLK_BPLL>,
249 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
250 <&clock CLK_MOUT_MCLK_CDREX>;
251 clock-names = "fout_spll",
259 samsung,syscon-clk = <&clock>;
264 compatible = "samsung,exynos5420-nocp";
270 compatible = "samsung,exynos5420-nocp";
276 compatible = "samsung,exynos5420-nocp";
282 compatible = "samsung,exynos5420-nocp";
288 compatible = "samsung,exynos5420-nocp";
294 compatible = "samsung,exynos5420-nocp";
300 compatible = "samsung,exynos-ppmu";
302 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
303 clock-names = "ppmu";
305 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
306 event-name = "ppmu-event3-dmc0-0";
312 compatible = "samsung,exynos-ppmu";
314 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
315 clock-names = "ppmu";
317 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
318 event-name = "ppmu-event3-dmc0-1";
324 compatible = "samsung,exynos-ppmu";
326 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
327 clock-names = "ppmu";
329 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
330 event-name = "ppmu-event3-dmc1-0";
336 compatible = "samsung,exynos-ppmu";
338 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
339 clock-names = "ppmu";
341 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
342 event-name = "ppmu-event3-dmc1-1";
347 gsc_pd: power-domain@10044000 {
348 compatible = "samsung,exynos4210-pd";
350 #power-domain-cells = <0>;
354 isp_pd: power-domain@10044020 {
355 compatible = "samsung,exynos4210-pd";
357 #power-domain-cells = <0>;
361 mfc_pd: power-domain@10044060 {
362 compatible = "samsung,exynos4210-pd";
364 #power-domain-cells = <0>;
368 g3d_pd: power-domain@10044080 {
369 compatible = "samsung,exynos4210-pd";
371 #power-domain-cells = <0>;
375 disp_pd: power-domain@100440c0 {
376 compatible = "samsung,exynos4210-pd";
378 #power-domain-cells = <0>;
382 mau_pd: power-domain@100440e0 {
383 compatible = "samsung,exynos4210-pd";
385 #power-domain-cells = <0>;
389 msc_pd: power-domain@10044120 {
390 compatible = "samsung,exynos4210-pd";
392 #power-domain-cells = <0>;
397 compatible = "samsung,exynos5420-pinctrl";
401 wakeup-interrupt-controller {
402 compatible = "samsung,exynos4210-wakeup-eint";
403 interrupt-parent = <&gic>;
409 compatible = "samsung,exynos5420-pinctrl";
415 compatible = "samsung,exynos5420-pinctrl";
421 compatible = "samsung,exynos5420-pinctrl";
427 compatible = "samsung,exynos5420-pinctrl";
430 power-domains = <&mau_pd>;
433 adma: dma-controller@3880000 {
438 clock-names = "apb_pclk";
439 #dma-cells = <1>;
440 power-domains = <&mau_pd>;
443 pdma0: dma-controller@121a0000 {
447 clocks = <&clock CLK_PDMA0>;
448 clock-names = "apb_pclk";
449 #dma-cells = <1>;
452 pdma1: dma-controller@121b0000 {
456 clocks = <&clock CLK_PDMA1>;
457 clock-names = "apb_pclk";
458 #dma-cells = <1>;
461 mdma0: dma-controller@10800000 {
465 clocks = <&clock CLK_MDMA0>;
466 clock-names = "apb_pclk";
467 #dma-cells = <1>;
470 mdma1: dma-controller@11c10000 {
474 clocks = <&clock CLK_MDMA1>;
475 clock-names = "apb_pclk";
476 #dma-cells = <1>;
478 * MDMA1 can support both secure and non-secure
488 compatible = "samsung,exynos5420-i2s";
493 dma-names = "tx", "rx", "tx-sec";
497 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
498 #clock-cells = <1>;
499 clock-output-names = "i2s_cdclk0";
500 #sound-dai-cells = <1>;
501 samsung,idma-addr = <0x03000000>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&i2s0_bus>;
504 power-domains = <&mau_pd>;
509 compatible = "samsung,exynos5420-i2s";
513 dma-names = "tx", "rx";
514 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
515 clock-names = "iis", "i2s_opclk0";
516 #clock-cells = <1>;
517 clock-output-names = "i2s_cdclk1";
518 #sound-dai-cells = <1>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2s1_bus>;
525 compatible = "samsung,exynos5420-i2s";
529 dma-names = "tx", "rx";
530 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
531 clock-names = "iis", "i2s_opclk0";
532 #clock-cells = <1>;
533 clock-output-names = "i2s_cdclk2";
534 #sound-dai-cells = <1>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2s2_bus>;
541 compatible = "samsung,exynos4210-spi";
546 dma-names = "tx", "rx";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&spi0_bus>;
551 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
552 clock-names = "spi", "spi_busclk0";
557 compatible = "samsung,exynos4210-spi";
562 dma-names = "tx", "rx";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&spi1_bus>;
567 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
568 clock-names = "spi", "spi_busclk0";
573 compatible = "samsung,exynos4210-spi";
578 dma-names = "tx", "rx";
579 #address-cells = <1>;
580 #size-cells = <0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&spi2_bus>;
583 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
584 clock-names = "spi", "spi_busclk0";
588 dp_phy: dp-video-phy {
589 compatible = "samsung,exynos5420-dp-video-phy";
590 samsung,pmu-syscon = <&pmu_system_controller>;
591 #phy-cells = <0>;
594 mipi_phy: mipi-video-phy {
595 compatible = "samsung,s5pv210-mipi-video-phy";
597 #phy-cells = <1>;
601 compatible = "samsung,exynos5410-mipi-dsi";
605 phy-names = "dsim";
606 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
607 clock-names = "bus_clk", "pll_clk";
608 #address-cells = <1>;
609 #size-cells = <0>;
614 compatible = "samsung,exynos5250-hsi2c";
617 #address-cells = <1>;
618 #size-cells = <0>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c8_hs_bus>;
621 clocks = <&clock CLK_USI4>;
622 clock-names = "hsi2c";
627 compatible = "samsung,exynos5250-hsi2c";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c9_hs_bus>;
634 clocks = <&clock CLK_USI5>;
635 clock-names = "hsi2c";
640 compatible = "samsung,exynos5250-hsi2c";
643 #address-cells = <1>;
644 #size-cells = <0>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c10_hs_bus>;
647 clocks = <&clock CLK_USI6>;
648 clock-names = "hsi2c";
653 compatible = "samsung,exynos5420-hdmi";
656 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
657 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
658 <&clock CLK_MOUT_HDMI>;
659 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
662 samsung,syscon-phandle = <&pmu_system_controller>;
664 power-domains = <&disp_pd>;
665 #sound-dai-cells = <0>;
673 compatible = "samsung,s5p-cec";
676 clocks = <&clock CLK_HDMI_CEC>;
677 clock-names = "hdmicec";
678 samsung,syscon-phandle = <&pmu_system_controller>;
679 hdmi-phandle = <&hdmi>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&hdmi_cec>;
686 compatible = "samsung,exynos5420-mixer";
689 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
690 <&clock CLK_SCLK_HDMI>;
691 clock-names = "mixer", "hdmi", "sclk_hdmi";
692 power-domains = <&disp_pd>;
698 compatible = "samsung,exynos5250-rotator";
701 clocks = <&clock CLK_ROTATOR>;
702 clock-names = "rotator";
706 gsc_0: video-scaler@13e00000 {
707 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
710 clocks = <&clock CLK_GSCL0>;
711 clock-names = "gscl";
712 power-domains = <&gsc_pd>;
716 gsc_1: video-scaler@13e10000 {
717 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
720 clocks = <&clock CLK_GSCL1>;
721 clock-names = "gscl";
722 power-domains = <&gsc_pd>;
727 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
732 interrupt-names = "job", "mmu", "gpu";
734 clocks = <&clock CLK_G3D>;
735 clock-names = "core";
736 power-domains = <&g3d_pd>;
737 operating-points-v2 = <&gpu_opp_table>;
740 #cooling-cells = <2>;
742 gpu_opp_table: opp-table {
743 compatible = "operating-points-v2";
745 opp-177000000 {
746 opp-hz = /bits/ 64 <177000000>;
747 opp-microvolt = <812500>;
749 opp-266000000 {
750 opp-hz = /bits/ 64 <266000000>;
751 opp-microvolt = <862500>;
753 opp-350000000 {
754 opp-hz = /bits/ 64 <350000000>;
755 opp-microvolt = <912500>;
757 opp-420000000 {
758 opp-hz = /bits/ 64 <420000000>;
759 opp-microvolt = <962500>;
761 opp-480000000 {
762 opp-hz = /bits/ 64 <480000000>;
763 opp-microvolt = <1000000>;
765 opp-543000000 {
766 opp-hz = /bits/ 64 <543000000>;
767 opp-microvolt = <1037500>;
769 opp-600000000 {
770 opp-hz = /bits/ 64 <600000000>;
771 opp-microvolt = <1150000>;
777 compatible = "samsung,exynos5420-scaler";
780 clocks = <&clock CLK_MSCL0>;
781 clock-names = "mscl";
782 power-domains = <&msc_pd>;
787 compatible = "samsung,exynos5420-scaler";
790 clocks = <&clock CLK_MSCL1>;
791 clock-names = "mscl";
792 power-domains = <&msc_pd>;
797 compatible = "samsung,exynos5420-scaler";
800 clocks = <&clock CLK_MSCL2>;
801 clock-names = "mscl";
802 power-domains = <&msc_pd>;
807 compatible = "samsung,exynos5420-jpeg";
810 clock-names = "jpeg";
811 clocks = <&clock CLK_JPEG>;
816 compatible = "samsung,exynos5420-jpeg";
819 clock-names = "jpeg";
820 clocks = <&clock CLK_JPEG2>;
824 pmu_system_controller: system-controller@10040000 {
825 compatible = "samsung,exynos5420-pmu", "syscon";
827 clock-names = "clkout16";
828 clocks = <&clock CLK_FIN_PLL>;
829 #clock-cells = <1>;
830 interrupt-controller;
831 #interrupt-cells = <3>;
832 interrupt-parent = <&gic>;
836 compatible = "samsung,exynos5420-tmu";
839 clocks = <&clock CLK_TMU>;
840 clock-names = "tmu_apbif";
841 #thermal-sensor-cells = <0>;
845 compatible = "samsung,exynos5420-tmu";
848 clocks = <&clock CLK_TMU>;
849 clock-names = "tmu_apbif";
850 #thermal-sensor-cells = <0>;
854 compatible = "samsung,exynos5420-tmu-ext-triminfo";
857 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
858 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
859 #thermal-sensor-cells = <0>;
863 compatible = "samsung,exynos5420-tmu-ext-triminfo";
866 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
867 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
868 #thermal-sensor-cells = <0>;
872 compatible = "samsung,exynos5420-tmu-ext-triminfo";
875 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
876 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
877 #thermal-sensor-cells = <0>;
881 compatible = "samsung,exynos-sysmmu";
883 interrupt-parent = <&combiner>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
887 #iommu-cells = <0>;
891 compatible = "samsung,exynos-sysmmu";
893 interrupt-parent = <&combiner>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
897 #iommu-cells = <0>;
901 compatible = "samsung,exynos-sysmmu";
903 interrupt-parent = <&combiner>;
905 clock-names = "sysmmu", "master";
906 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
907 power-domains = <&disp_pd>;
908 #iommu-cells = <0>;
912 compatible = "samsung,exynos-sysmmu";
914 interrupt-parent = <&combiner>;
916 clock-names = "sysmmu", "master";
917 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
918 power-domains = <&gsc_pd>;
919 #iommu-cells = <0>;
923 compatible = "samsung,exynos-sysmmu";
925 interrupt-parent = <&combiner>;
927 clock-names = "sysmmu", "master";
928 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
929 power-domains = <&gsc_pd>;
930 #iommu-cells = <0>;
934 compatible = "samsung,exynos-sysmmu";
936 interrupt-parent = <&combiner>;
938 clock-names = "sysmmu", "master";
939 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
940 power-domains = <&msc_pd>;
941 #iommu-cells = <0>;
945 compatible = "samsung,exynos-sysmmu";
948 clock-names = "sysmmu", "master";
949 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
950 power-domains = <&msc_pd>;
951 #iommu-cells = <0>;
955 compatible = "samsung,exynos-sysmmu";
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
960 power-domains = <&msc_pd>;
961 #iommu-cells = <0>;
965 compatible = "samsung,exynos-sysmmu";
967 interrupt-parent = <&combiner>;
969 clock-names = "sysmmu", "master";
970 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
971 power-domains = <&msc_pd>;
972 #iommu-cells = <0>;
976 compatible = "samsung,exynos-sysmmu";
978 interrupt-parent = <&combiner>;
980 clock-names = "sysmmu", "master";
981 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
982 power-domains = <&msc_pd>;
983 #iommu-cells = <0>;
987 compatible = "samsung,exynos-sysmmu";
989 interrupt-parent = <&combiner>;
991 clock-names = "sysmmu", "master";
992 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
993 power-domains = <&msc_pd>;
994 #iommu-cells = <0>;
998 compatible = "samsung,exynos-sysmmu";
1000 interrupt-parent = <&combiner>;
1002 clock-names = "sysmmu", "master";
1003 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1004 #iommu-cells = <0>;
1008 compatible = "samsung,exynos-sysmmu";
1010 interrupt-parent = <&combiner>;
1012 clock-names = "sysmmu", "master";
1013 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1014 #iommu-cells = <0>;
1018 compatible = "samsung,exynos-sysmmu";
1021 clock-names = "sysmmu", "master";
1022 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1023 #iommu-cells = <0>;
1027 compatible = "samsung,exynos-sysmmu";
1029 interrupt-parent = <&combiner>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1033 power-domains = <&mfc_pd>;
1034 #iommu-cells = <0>;
1038 compatible = "samsung,exynos-sysmmu";
1040 interrupt-parent = <&combiner>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1044 power-domains = <&mfc_pd>;
1045 #iommu-cells = <0>;
1049 compatible = "samsung,exynos-sysmmu";
1051 interrupt-parent = <&combiner>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1055 power-domains = <&disp_pd>;
1056 #iommu-cells = <0>;
1060 compatible = "samsung,exynos-sysmmu";
1062 interrupt-parent = <&combiner>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1066 power-domains = <&disp_pd>;
1067 #iommu-cells = <0>;
1070 bus_wcore: bus-wcore {
1071 compatible = "samsung,exynos-bus";
1072 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1073 clock-names = "bus";
1077 bus_noc: bus-noc {
1078 compatible = "samsung,exynos-bus";
1079 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1080 clock-names = "bus";
1084 bus_fsys_apb: bus-fsys-apb {
1085 compatible = "samsung,exynos-bus";
1086 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1087 clock-names = "bus";
1091 bus_fsys: bus-fsys {
1092 compatible = "samsung,exynos-bus";
1093 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1094 clock-names = "bus";
1098 bus_fsys2: bus-fsys2 {
1099 compatible = "samsung,exynos-bus";
1100 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1101 clock-names = "bus";
1105 bus_mfc: bus-mfc {
1106 compatible = "samsung,exynos-bus";
1107 clocks = <&clock CLK_DOUT_ACLK333>;
1108 clock-names = "bus";
1112 bus_gen: bus-gen {
1113 compatible = "samsung,exynos-bus";
1114 clocks = <&clock CLK_DOUT_ACLK266>;
1115 clock-names = "bus";
1119 bus_peri: bus-peri {
1120 compatible = "samsung,exynos-bus";
1121 clocks = <&clock CLK_DOUT_ACLK66>;
1122 clock-names = "bus";
1126 bus_g2d: bus-g2d {
1127 compatible = "samsung,exynos-bus";
1128 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1129 clock-names = "bus";
1133 bus_g2d_acp: bus-g2d-acp {
1134 compatible = "samsung,exynos-bus";
1135 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1136 clock-names = "bus";
1140 bus_jpeg: bus-jpeg {
1141 compatible = "samsung,exynos-bus";
1142 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1143 clock-names = "bus";
1147 bus_jpeg_apb: bus-jpeg-apb {
1148 compatible = "samsung,exynos-bus";
1149 clocks = <&clock CLK_DOUT_ACLK166>;
1150 clock-names = "bus";
1154 bus_disp1_fimd: bus-disp1-fimd {
1155 compatible = "samsung,exynos-bus";
1156 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1157 clock-names = "bus";
1161 bus_disp1: bus-disp1 {
1162 compatible = "samsung,exynos-bus";
1163 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1164 clock-names = "bus";
1168 bus_gscl_scaler: bus-gscl-scaler {
1169 compatible = "samsung,exynos-bus";
1170 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1171 clock-names = "bus";
1175 bus_mscl: bus-mscl {
1176 compatible = "samsung,exynos-bus";
1177 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1178 clock-names = "bus";
1183 thermal-zones {
1184 cpu0_thermal: cpu0-thermal {
1185 thermal-sensors = <&tmu_cpu0>;
1186 #include "exynos5420-trip-points.dtsi"
1188 cpu1_thermal: cpu1-thermal {
1189 thermal-sensors = <&tmu_cpu1>;
1190 #include "exynos5420-trip-points.dtsi"
1192 cpu2_thermal: cpu2-thermal {
1193 thermal-sensors = <&tmu_cpu2>;
1194 #include "exynos5420-trip-points.dtsi"
1196 cpu3_thermal: cpu3-thermal {
1197 thermal-sensors = <&tmu_cpu3>;
1198 #include "exynos5420-trip-points.dtsi"
1200 gpu_thermal: gpu-thermal {
1201 thermal-sensors = <&tmu_gpu>;
1202 #include "exynos5420-trip-points.dtsi"
1208 clocks = <&clock CLK_TSADC>;
1209 clock-names = "adc";
1210 samsung,syscon-phandle = <&pmu_system_controller>;
1214 clocks = <&clock CLK_DP1>;
1215 clock-names = "dp";
1217 phy-names = "dp";
1218 power-domains = <&disp_pd>;
1222 compatible = "samsung,exynos5420-fimd";
1223 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1224 clock-names = "sclk_fimd", "fimd";
1225 power-domains = <&disp_pd>;
1227 iommu-names = "m0", "m1";
1232 clocks = <&clock CLK_G2D>;
1233 clock-names = "fimg2d";
1238 clocks = <&clock CLK_I2C0>;
1239 clock-names = "i2c";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&i2c0_bus>;
1245 clocks = <&clock CLK_I2C1>;
1246 clock-names = "i2c";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&i2c1_bus>;
1252 clocks = <&clock CLK_I2C2>;
1253 clock-names = "i2c";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&i2c2_bus>;
1259 clocks = <&clock CLK_I2C3>;
1260 clock-names = "i2c";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&i2c3_bus>;
1266 clocks = <&clock CLK_USI0>;
1267 clock-names = "hsi2c";
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&i2c4_hs_bus>;
1273 clocks = <&clock CLK_USI1>;
1274 clock-names = "hsi2c";
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&i2c5_hs_bus>;
1280 clocks = <&clock CLK_USI2>;
1281 clock-names = "hsi2c";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&i2c6_hs_bus>;
1287 clocks = <&clock CLK_USI3>;
1288 clock-names = "hsi2c";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&i2c7_hs_bus>;
1294 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1295 clock-names = "fin_pll", "mct";
1299 clocks = <&clock CLK_SSS>;
1300 clock-names = "secss";
1304 clocks = <&clock CLK_PWM>;
1305 clock-names = "timers";
1309 clocks = <&clock CLK_RTC>;
1310 clock-names = "rtc";
1311 interrupt-parent = <&pmu_system_controller>;
1316 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1317 clock-names = "uart", "clk_uart_baud0";
1319 dma-names = "rx", "tx";
1323 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1324 clock-names = "uart", "clk_uart_baud0";
1326 dma-names = "rx", "tx";
1330 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1331 clock-names = "uart", "clk_uart_baud0";
1333 dma-names = "rx", "tx";
1337 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1338 clock-names = "uart", "clk_uart_baud0";
1340 dma-names = "rx", "tx";
1344 clocks = <&clock CLK_SSS>;
1345 clock-names = "secss";
1349 clocks = <&clock CLK_SSS>;
1350 clock-names = "secss";
1354 clocks = <&clock CLK_USBD300>;
1355 clock-names = "usbdrd30";
1359 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1360 clock-names = "phy", "ref";
1361 samsung,pmu-syscon = <&pmu_system_controller>;
1365 clocks = <&clock CLK_USBD301>;
1366 clock-names = "usbdrd30";
1374 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1375 clock-names = "phy", "ref";
1376 samsung,pmu-syscon = <&pmu_system_controller>;
1380 clocks = <&clock CLK_USBH20>;
1381 clock-names = "usbhost";
1385 clocks = <&clock CLK_USBH20>;
1386 clock-names = "usbhost";
1390 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1391 clock-names = "phy", "ref";
1392 samsung,sysreg-phandle = <&sysreg_system_controller>;
1393 samsung,pmureg-phandle = <&pmu_system_controller>;
1397 clocks = <&clock CLK_WDT>;
1398 clock-names = "watchdog";
1399 samsung,syscon-phandle = <&pmu_system_controller>;
1402 #include "exynos5420-pinctrl.dtsi"
1403 #include "exynos-syscon-restart.dtsi"