Lines Matching +full:opp +full:- +full:600000000
1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
38 cpu-map {
57 compatible = "arm,cortex-a9";
60 clock-names = "cpu";
61 operating-points-v2 = <&cpu0_opp_table>;
62 #cooling-cells = <2>; /* min followed by max */
67 compatible = "arm,cortex-a9";
70 clock-names = "cpu";
71 operating-points-v2 = <&cpu0_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
77 compatible = "arm,cortex-a9";
80 clock-names = "cpu";
81 operating-points-v2 = <&cpu0_opp_table>;
82 #cooling-cells = <2>; /* min followed by max */
87 compatible = "arm,cortex-a9";
90 clock-names = "cpu";
91 operating-points-v2 = <&cpu0_opp_table>;
92 #cooling-cells = <2>; /* min followed by max */
96 cpu0_opp_table: opp-table0 {
97 compatible = "operating-points-v2";
98 opp-shared;
100 opp-200000000 {
101 opp-hz = /bits/ 64 <200000000>;
102 opp-microvolt = <900000>;
103 clock-latency-ns = <200000>;
105 opp-300000000 {
106 opp-hz = /bits/ 64 <300000000>;
107 opp-microvolt = <900000>;
108 clock-latency-ns = <200000>;
110 opp-400000000 {
111 opp-hz = /bits/ 64 <400000000>;
112 opp-microvolt = <925000>;
113 clock-latency-ns = <200000>;
115 opp-500000000 {
116 opp-hz = /bits/ 64 <500000000>;
117 opp-microvolt = <950000>;
118 clock-latency-ns = <200000>;
120 opp-600000000 {
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <975000>;
123 clock-latency-ns = <200000>;
125 opp-700000000 {
126 opp-hz = /bits/ 64 <700000000>;
127 opp-microvolt = <987500>;
128 clock-latency-ns = <200000>;
130 opp-800000000 {
131 opp-hz = /bits/ 64 <800000000>;
132 opp-microvolt = <1000000>;
133 clock-latency-ns = <200000>;
134 opp-suspend;
136 opp-900000000 {
137 opp-hz = /bits/ 64 <900000000>;
138 opp-microvolt = <1037500>;
139 clock-latency-ns = <200000>;
141 opp-1000000000 {
142 opp-hz = /bits/ 64 <1000000000>;
143 opp-microvolt = <1087500>;
144 clock-latency-ns = <200000>;
146 opp-1100000000 {
147 opp-hz = /bits/ 64 <1100000000>;
148 opp-microvolt = <1137500>;
149 clock-latency-ns = <200000>;
151 opp-1200000000 {
152 opp-hz = /bits/ 64 <1200000000>;
153 opp-microvolt = <1187500>;
154 clock-latency-ns = <200000>;
156 opp-1300000000 {
157 opp-hz = /bits/ 64 <1300000000>;
158 opp-microvolt = <1250000>;
159 clock-latency-ns = <200000>;
161 opp-1400000000 {
162 opp-hz = /bits/ 64 <1400000000>;
163 opp-microvolt = <1287500>;
164 clock-latency-ns = <200000>;
166 cpu0_opp_1500: opp-1500000000 {
167 opp-hz = /bits/ 64 <1500000000>;
168 opp-microvolt = <1350000>;
169 clock-latency-ns = <200000>;
170 turbo-mode;
178 compatible = "samsung,exynos4x12-pinctrl";
184 compatible = "samsung,exynos4x12-pinctrl";
188 wakup_eint: wakeup-interrupt-controller {
189 compatible = "samsung,exynos4210-wakeup-eint";
190 interrupt-parent = <&gic>;
196 compatible = "samsung,exynos4x12-pinctrl";
198 interrupt-parent = <&combiner>;
203 compatible = "samsung,exynos4x12-pinctrl";
209 compatible = "mmio-sram";
211 #address-cells = <1>;
212 #size-cells = <1>;
215 smp-sram@0 {
216 compatible = "samsung,exynos4210-sysram";
220 smp-sram@2f000 {
221 compatible = "samsung,exynos4210-sysram-ns";
226 pd_isp: power-domain@10023ca0 {
227 compatible = "samsung,exynos4210-pd";
229 #power-domain-cells = <0>;
233 l2c: cache-controller@10502000 {
234 compatible = "arm,pl310-cache";
236 cache-unified;
237 cache-level = <2>;
238 prefetch-data = <1>;
239 prefetch-instr = <1>;
240 arm,tag-latency = <2 2 1>;
241 arm,data-latency = <3 2 1>;
242 arm,double-linefill = <1>;
243 arm,double-linefill-incr = <0>;
244 arm,double-linefill-wrap = <1>;
245 arm,prefetch-drop = <1>;
246 arm,prefetch-offset = <7>;
249 clock: clock-controller@10030000 {
250 compatible = "samsung,exynos4412-clock";
252 #clock-cells = <1>;
255 isp_clock: clock-controller@10048000 {
256 compatible = "samsung,exynos4412-isp-clock";
258 #clock-cells = <1>;
259 power-domains = <&pd_isp>;
262 clock-names = "aclk200", "aclk400_mcuisp";
266 compatible = "samsung,exynos4412-mct";
269 clock-names = "fin_pll", "mct";
270 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
278 compatible = "samsung,exynos5250-wdt";
282 clock-names = "watchdog";
283 samsung,syscon-phandle = <&pmu_system_controller>;
287 compatible = "samsung,exynos4212-adc";
289 interrupt-parent = <&combiner>;
292 clock-names = "adc";
293 #io-channel-cells = <1>;
294 samsung,syscon-phandle = <&pmu_system_controller>;
299 compatible = "samsung,exynos4212-g2d";
303 clock-names = "sclk_fimg2d", "fimg2d";
308 compatible = "samsung,exynos4412-dw-mshc";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 fifo-depth = <0x80>;
315 clock-names = "biu", "ciu";
320 compatible = "samsung,exynos-sysmmu";
322 interrupt-parent = <&combiner>;
324 clock-names = "sysmmu", "master";
326 #iommu-cells = <0>;
330 compatible = "samsung,exynos-sysmmu";
332 interrupt-parent = <&combiner>;
334 power-domains = <&pd_isp>;
335 clock-names = "sysmmu";
337 #iommu-cells = <0>;
341 compatible = "samsung,exynos-sysmmu";
343 interrupt-parent = <&combiner>;
345 power-domains = <&pd_isp>;
346 clock-names = "sysmmu";
348 #iommu-cells = <0>;
352 compatible = "samsung,exynos-sysmmu";
354 interrupt-parent = <&combiner>;
356 power-domains = <&pd_isp>;
357 clock-names = "sysmmu";
359 #iommu-cells = <0>;
363 compatible = "samsung,exynos-sysmmu";
365 interrupt-parent = <&combiner>;
367 power-domains = <&pd_isp>;
368 clock-names = "sysmmu";
370 #iommu-cells = <0>;
374 compatible = "samsung,exynos-sysmmu";
376 interrupt-parent = <&combiner>;
378 power-domains = <&pd_isp>;
379 clock-names = "sysmmu", "master";
382 #iommu-cells = <0>;
386 compatible = "samsung,exynos-sysmmu";
388 interrupt-parent = <&combiner>;
390 power-domains = <&pd_isp>;
391 clock-names = "sysmmu", "master";
394 #iommu-cells = <0>;
397 bus_dmc: bus-dmc {
398 compatible = "samsung,exynos-bus";
400 clock-names = "bus";
401 operating-points-v2 = <&bus_dmc_opp_table>;
402 samsung,data-clock-ratio = <4>;
403 #interconnect-cells = <0>;
407 bus_acp: bus-acp {
408 compatible = "samsung,exynos-bus";
410 clock-names = "bus";
411 operating-points-v2 = <&bus_acp_opp_table>;
415 bus_c2c: bus-c2c {
416 compatible = "samsung,exynos-bus";
418 clock-names = "bus";
419 operating-points-v2 = <&bus_dmc_opp_table>;
423 bus_dmc_opp_table: opp-table1 {
424 compatible = "operating-points-v2";
426 opp-100000000 {
427 opp-hz = /bits/ 64 <100000000>;
428 opp-microvolt = <900000>;
430 opp-134000000 {
431 opp-hz = /bits/ 64 <134000000>;
432 opp-microvolt = <900000>;
434 opp-160000000 {
435 opp-hz = /bits/ 64 <160000000>;
436 opp-microvolt = <900000>;
438 opp-267000000 {
439 opp-hz = /bits/ 64 <267000000>;
440 opp-microvolt = <950000>;
442 opp-400000000 {
443 opp-hz = /bits/ 64 <400000000>;
444 opp-microvolt = <1050000>;
445 opp-suspend;
449 bus_acp_opp_table: opp-table2 {
450 compatible = "operating-points-v2";
452 opp-100000000 {
453 opp-hz = /bits/ 64 <100000000>;
455 opp-134000000 {
456 opp-hz = /bits/ 64 <134000000>;
458 opp-160000000 {
459 opp-hz = /bits/ 64 <160000000>;
461 opp-267000000 {
462 opp-hz = /bits/ 64 <267000000>;
466 bus_leftbus: bus-leftbus {
467 compatible = "samsung,exynos-bus";
469 clock-names = "bus";
470 operating-points-v2 = <&bus_leftbus_opp_table>;
472 #interconnect-cells = <0>;
476 bus_rightbus: bus-rightbus {
477 compatible = "samsung,exynos-bus";
479 clock-names = "bus";
480 operating-points-v2 = <&bus_leftbus_opp_table>;
484 bus_display: bus-display {
485 compatible = "samsung,exynos-bus";
487 clock-names = "bus";
488 operating-points-v2 = <&bus_display_opp_table>;
490 #interconnect-cells = <0>;
494 bus_fsys: bus-fsys {
495 compatible = "samsung,exynos-bus";
497 clock-names = "bus";
498 operating-points-v2 = <&bus_fsys_opp_table>;
502 bus_peri: bus-peri {
503 compatible = "samsung,exynos-bus";
505 clock-names = "bus";
506 operating-points-v2 = <&bus_peri_opp_table>;
510 bus_mfc: bus-mfc {
511 compatible = "samsung,exynos-bus";
513 clock-names = "bus";
514 operating-points-v2 = <&bus_leftbus_opp_table>;
518 bus_leftbus_opp_table: opp-table3 {
519 compatible = "operating-points-v2";
521 opp-100000000 {
522 opp-hz = /bits/ 64 <100000000>;
523 opp-microvolt = <900000>;
525 opp-134000000 {
526 opp-hz = /bits/ 64 <134000000>;
527 opp-microvolt = <925000>;
529 opp-160000000 {
530 opp-hz = /bits/ 64 <160000000>;
531 opp-microvolt = <950000>;
533 opp-200000000 {
534 opp-hz = /bits/ 64 <200000000>;
535 opp-microvolt = <1000000>;
536 opp-suspend;
540 bus_display_opp_table: opp-table4 {
541 compatible = "operating-points-v2";
543 opp-160000000 {
544 opp-hz = /bits/ 64 <160000000>;
546 opp-200000000 {
547 opp-hz = /bits/ 64 <200000000>;
551 bus_fsys_opp_table: opp-table5 {
552 compatible = "operating-points-v2";
554 opp-100000000 {
555 opp-hz = /bits/ 64 <100000000>;
557 opp-134000000 {
558 opp-hz = /bits/ 64 <134000000>;
562 bus_peri_opp_table: opp-table6 {
563 compatible = "operating-points-v2";
565 opp-50000000 {
566 opp-hz = /bits/ 64 <50000000>;
568 opp-100000000 {
569 opp-hz = /bits/ 64 <100000000>;
576 samsung,combiner-nr = <20>;
602 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
604 /* fimc_[0-3] are configured outside, under phandles */
605 fimc_lite_0: fimc-lite@12390000 {
606 compatible = "samsung,exynos4212-fimc-lite";
609 power-domains = <&pd_isp>;
611 clock-names = "flite";
616 fimc_lite_1: fimc-lite@123a0000 {
617 compatible = "samsung,exynos4212-fimc-lite";
620 power-domains = <&pd_isp>;
622 clock-names = "flite";
627 fimc_is: fimc-is@12000000 {
628 compatible = "samsung,exynos4212-fimc-is";
632 power-domains = <&pd_isp>;
654 clock-names = "lite0", "lite1", "ppmuispx",
664 iommu-names = "isp", "drc", "fd", "mcuctl";
665 #address-cells = <1>;
666 #size-cells = <1>;
674 i2c1_isp: i2c-isp@12140000 {
675 compatible = "samsung,exynos4212-i2c-isp";
678 clock-names = "i2c_isp";
679 #address-cells = <1>;
680 #size-cells = <0>;
686 compatible = "samsung,exynos4x12-usb2-phy";
687 samsung,sysreg-phandle = <&sys_reg>;
691 compatible = "samsung,exynos4212-fimc";
692 samsung,pix-limits = <4224 8192 1920 4224>;
693 samsung,mainscaler-ext;
694 samsung,isp-wb;
695 samsung,cam-if;
699 compatible = "samsung,exynos4212-fimc";
700 samsung,pix-limits = <4224 8192 1920 4224>;
701 samsung,mainscaler-ext;
702 samsung,isp-wb;
703 samsung,cam-if;
707 compatible = "samsung,exynos4212-fimc";
708 samsung,pix-limits = <4224 8192 1920 4224>;
709 samsung,mainscaler-ext;
710 samsung,isp-wb;
711 samsung,lcd-wb;
712 samsung,cam-if;
716 compatible = "samsung,exynos4212-fimc";
717 samsung,pix-limits = <1920 8192 1366 1920>;
719 samsung,mainscaler-ext;
720 samsung,isp-wb;
721 samsung,lcd-wb;
725 cpu-offset = <0x4000>;
740 interrupt-names = "gp",
751 operating-points-v2 = <&gpu_opp_table>;
753 gpu_opp_table: opp-table {
754 compatible = "operating-points-v2";
756 opp-160000000 {
757 opp-hz = /bits/ 64 <160000000>;
758 opp-microvolt = <875000>;
760 opp-267000000 {
761 opp-hz = /bits/ 64 <267000000>;
762 opp-microvolt = <900000>;
764 opp-350000000 {
765 opp-hz = /bits/ 64 <350000000>;
766 opp-microvolt = <950000>;
768 opp-440000000 {
769 opp-hz = /bits/ 64 <440000000>;
770 opp-microvolt = <1025000>;
776 compatible = "samsung,exynos4212-hdmi";
780 compatible = "samsung,exynos4212-jpeg";
784 compatible = "samsung,exynos4212-rotator";
788 compatible = "samsung,exynos4212-mixer";
789 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
797 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
802 compatible = "samsung,exynos4412-pmu", "syscon";
803 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
808 #clock-cells = <1>;
812 compatible = "samsung,exynos4412-tmu";
813 interrupt-parent = <&combiner>;
817 clock-names = "tmu_apbif";
821 #include "exynos4412-pinctrl.dtsi"