Lines Matching +full:0 +full:x11400000
36 #size-cells = <0>;
58 reg = <0xA00>;
68 reg = <0xA01>;
78 reg = <0xA02>;
88 reg = <0xA03>;
179 reg = <0x11400000 0x1000>;
185 reg = <0x11000000 0x1000>;
197 reg = <0x03860000 0x1000>;
199 interrupts = <10 0>;
204 reg = <0x106E0000 0x1000>;
210 reg = <0x02020000 0x40000>;
213 ranges = <0 0x02020000 0x40000>;
215 smp-sram@0 {
217 reg = <0x0 0x1000>;
222 reg = <0x2f000 0x1000>;
228 reg = <0x10023CA0 0x20>;
229 #power-domain-cells = <0>;
235 reg = <0x10502000 0x1000>;
243 arm,double-linefill-incr = <0>;
251 reg = <0x10030000 0x18000>;
257 reg = <0x10048000 0x1000>;
267 reg = <0x10050000 0x800>;
279 reg = <0x10060000 0x100>;
288 reg = <0x126C0000 0x100>;
300 reg = <0x10800000 0x1000>;
309 reg = <0x12550000 0x1000>;
312 #size-cells = <0>;
313 fifo-depth = <0x80>;
321 reg = <0x10A40000 0x1000>;
326 #iommu-cells = <0>;
331 reg = <0x12260000 0x1000>;
337 #iommu-cells = <0>;
342 reg = <0x12270000 0x1000>;
348 #iommu-cells = <0>;
353 reg = <0x122A0000 0x1000>;
359 #iommu-cells = <0>;
364 reg = <0x122B0000 0x1000>;
370 #iommu-cells = <0>;
375 reg = <0x123B0000 0x1000>;
377 interrupts = <16 0>;
382 #iommu-cells = <0>;
387 reg = <0x123C0000 0x1000>;
394 #iommu-cells = <0>;
403 #interconnect-cells = <0>;
472 #interconnect-cells = <0>;
490 #interconnect-cells = <0>;
577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
604 /* fimc_[0-3] are configured outside, under phandles */
607 reg = <0x12390000 0x1000>;
618 reg = <0x123A0000 0x1000>;
629 reg = <0x12000000 0x260000>;
671 reg = <0x10020000 0x3000>;
676 reg = <0x12140000 0x100>;
680 #size-cells = <0>;
718 samsung,rotators = <0>;
725 cpu-offset = <0x4000>;
815 reg = <0x100C0000 0x100>;