Lines Matching +full:exynos4210 +full:- +full:mct
1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC device tree source
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
20 #include "exynos4-cpu-thermal.dtsi"
23 compatible = "samsung,exynos4210", "samsung,exynos4";
32 #address-cells = <1>;
33 #size-cells = <0>;
35 cpu-map {
48 compatible = "arm,cortex-a9";
51 clock-names = "cpu";
52 clock-latency = <160000>;
54 operating-points = <
62 #cooling-cells = <2>; /* min followed by max */
67 compatible = "arm,cortex-a9";
70 clock-names = "cpu";
71 clock-latency = <160000>;
73 operating-points = <
81 #cooling-cells = <2>; /* min followed by max */
87 compatible = "mmio-sram";
89 #address-cells = <1>;
90 #size-cells = <1>;
93 smp-sram@0 {
94 compatible = "samsung,exynos4210-sysram";
98 smp-sram@1f000 {
99 compatible = "samsung,exynos4210-sysram-ns";
104 pd_lcd1: power-domain@10023ca0 {
105 compatible = "samsung,exynos4210-pd";
107 #power-domain-cells = <0>;
111 l2c: cache-controller@10502000 {
112 compatible = "arm,pl310-cache";
114 cache-unified;
115 cache-level = <2>;
116 prefetch-data = <1>;
117 prefetch-instr = <1>;
118 arm,tag-latency = <2 2 1>;
119 arm,data-latency = <2 2 1>;
122 mct: timer@10050000 { label
123 compatible = "samsung,exynos4210-mct";
126 clock-names = "fin_pll", "mct";
127 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
136 compatible = "samsung,s3c6410-wdt";
140 clock-names = "watchdog";
143 clock: clock-controller@10030000 {
144 compatible = "samsung,exynos4210-clock";
146 #clock-cells = <1>;
150 compatible = "samsung,exynos4210-pinctrl";
156 compatible = "samsung,exynos4210-pinctrl";
160 wakup_eint: wakeup-interrupt-controller {
161 compatible = "samsung,exynos4210-wakeup-eint";
162 interrupt-parent = <&gic>;
168 compatible = "samsung,exynos4210-pinctrl";
173 compatible = "samsung,s5pv210-g2d";
177 clock-names = "sclk_fimg2d", "fimg2d";
178 power-domains = <&pd_lcd0>;
183 compatible = "samsung,exynos-ppmu";
189 compatible = "samsung,exynos-ppmu";
192 clock-names = "ppmu";
197 compatible = "samsung,exynos-sysmmu";
199 interrupt-parent = <&combiner>;
201 clock-names = "sysmmu", "master";
203 power-domains = <&pd_lcd0>;
204 #iommu-cells = <0>;
208 compatible = "samsung,exynos-sysmmu";
209 interrupt-parent = <&combiner>;
212 clock-names = "sysmmu", "master";
214 power-domains = <&pd_lcd1>;
215 #iommu-cells = <0>;
218 bus_dmc: bus-dmc {
219 compatible = "samsung,exynos-bus";
221 clock-names = "bus";
222 operating-points-v2 = <&bus_dmc_opp_table>;
226 bus_acp: bus-acp {
227 compatible = "samsung,exynos-bus";
229 clock-names = "bus";
230 operating-points-v2 = <&bus_acp_opp_table>;
234 bus_peri: bus-peri {
235 compatible = "samsung,exynos-bus";
237 clock-names = "bus";
238 operating-points-v2 = <&bus_peri_opp_table>;
242 bus_fsys: bus-fsys {
243 compatible = "samsung,exynos-bus";
245 clock-names = "bus";
246 operating-points-v2 = <&bus_fsys_opp_table>;
250 bus_display: bus-display {
251 compatible = "samsung,exynos-bus";
253 clock-names = "bus";
254 operating-points-v2 = <&bus_display_opp_table>;
258 bus_lcd0: bus-lcd0 {
259 compatible = "samsung,exynos-bus";
261 clock-names = "bus";
262 operating-points-v2 = <&bus_leftbus_opp_table>;
266 bus_leftbus: bus-leftbus {
267 compatible = "samsung,exynos-bus";
269 clock-names = "bus";
270 operating-points-v2 = <&bus_leftbus_opp_table>;
274 bus_rightbus: bus-rightbus {
275 compatible = "samsung,exynos-bus";
277 clock-names = "bus";
278 operating-points-v2 = <&bus_leftbus_opp_table>;
282 bus_mfc: bus-mfc {
283 compatible = "samsung,exynos-bus";
285 clock-names = "bus";
286 operating-points-v2 = <&bus_leftbus_opp_table>;
290 bus_dmc_opp_table: opp-table1 {
291 compatible = "operating-points-v2";
292 opp-shared;
294 opp-134000000 {
295 opp-hz = /bits/ 64 <134000000>;
296 opp-microvolt = <1025000>;
298 opp-267000000 {
299 opp-hz = /bits/ 64 <267000000>;
300 opp-microvolt = <1050000>;
302 opp-400000000 {
303 opp-hz = /bits/ 64 <400000000>;
304 opp-microvolt = <1150000>;
305 opp-suspend;
309 bus_acp_opp_table: opp-table2 {
310 compatible = "operating-points-v2";
311 opp-shared;
313 opp-134000000 {
314 opp-hz = /bits/ 64 <134000000>;
316 opp-160000000 {
317 opp-hz = /bits/ 64 <160000000>;
319 opp-200000000 {
320 opp-hz = /bits/ 64 <200000000>;
324 bus_peri_opp_table: opp-table3 {
325 compatible = "operating-points-v2";
326 opp-shared;
328 opp-5000000 {
329 opp-hz = /bits/ 64 <5000000>;
331 opp-100000000 {
332 opp-hz = /bits/ 64 <100000000>;
336 bus_fsys_opp_table: opp-table4 {
337 compatible = "operating-points-v2";
338 opp-shared;
340 opp-10000000 {
341 opp-hz = /bits/ 64 <10000000>;
343 opp-134000000 {
344 opp-hz = /bits/ 64 <134000000>;
348 bus_display_opp_table: opp-table5 {
349 compatible = "operating-points-v2";
350 opp-shared;
352 opp-100000000 {
353 opp-hz = /bits/ 64 <100000000>;
355 opp-134000000 {
356 opp-hz = /bits/ 64 <134000000>;
358 opp-160000000 {
359 opp-hz = /bits/ 64 <160000000>;
363 bus_leftbus_opp_table: opp-table6 {
364 compatible = "operating-points-v2";
365 opp-shared;
367 opp-100000000 {
368 opp-hz = /bits/ 64 <100000000>;
370 opp-160000000 {
371 opp-hz = /bits/ 64 <160000000>;
373 opp-200000000 {
374 opp-hz = /bits/ 64 <200000000>;
375 opp-suspend;
394 polling-delay-passive = <0>;
395 polling-delay = <0>;
396 thermal-sensors = <&tmu 0>;
400 cpu-offset = <0x8000>;
406 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
410 samsung,combiner-nr = <16>;
430 samsung,pix-limits = <4224 8192 1920 4224>;
431 samsung,mainscaler-ext;
432 samsung,cam-if;
436 samsung,pix-limits = <4224 8192 1920 4224>;
437 samsung,mainscaler-ext;
438 samsung,cam-if;
442 samsung,pix-limits = <4224 8192 1920 4224>;
443 samsung,mainscaler-ext;
444 samsung,lcd-wb;
448 samsung,pix-limits = <1920 8192 1366 1920>;
450 samsung,mainscaler-ext;
451 samsung,lcd-wb;
465 interrupt-names = "gp",
475 operating-points-v2 = <&gpu_opp_table>;
477 gpu_opp_table: opp-table {
478 compatible = "operating-points-v2";
480 opp-160000000 {
481 opp-hz = /bits/ 64 <160000000>;
482 opp-microvolt = <950000>;
484 opp-267000000 {
485 opp-hz = /bits/ 64 <267000000>;
486 opp-microvolt = <1050000>;
492 power-domains = <&pd_lcd0>;
496 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
505 interrupt-affinity = <&cpu0>, <&cpu1>;
510 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
515 #clock-cells = <1>;
519 power-domains = <&pd_lcd0>;
523 power-domains = <&pd_lcd0>;
527 compatible = "samsung,exynos4210-tmu";
529 clock-names = "tmu_apbif";
532 #include "exynos4210-pinctrl.dtsi"