Lines Matching +full:exynos4210 +full:- +full:mct
1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
53 cpu-map {
66 compatible = "arm,cortex-a7";
68 clock-frequency = <1000000000>;
70 clock-names = "cpu";
71 #cooling-cells = <2>;
73 operating-points = <
89 compatible = "arm,cortex-a7";
91 clock-frequency = <1000000000>;
93 clock-names = "cpu";
94 #cooling-cells = <2>;
96 operating-points = <
111 xusbxti: clock-0 {
112 compatible = "fixed-clock";
113 clock-frequency = <0>;
114 #clock-cells = <0>;
115 clock-output-names = "xusbxti";
118 xxti: clock-1 {
119 compatible = "fixed-clock";
120 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-output-names = "xxti";
125 xtcxo: clock-2 {
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-output-names = "xtcxo";
133 compatible = "arm,cortex-a7-pmu";
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
145 compatible = "mmio-sram";
147 #address-cells = <1>;
148 #size-cells = <1>;
151 smp-sram@0 {
152 compatible = "samsung,exynos4210-sysram";
156 smp-sram@3f000 {
157 compatible = "samsung,exynos4210-sysram-ns";
163 compatible = "samsung,exynos4210-chipid";
168 compatible = "samsung,exynos3-sysreg", "syscon";
172 pmu_system_controller: system-controller@10020000 {
173 compatible = "samsung,exynos3250-pmu", "syscon";
175 interrupt-controller;
176 #interrupt-cells = <3>;
177 interrupt-parent = <&gic>;
178 clock-names = "clkout8";
180 #clock-cells = <1>;
183 mipi_phy: video-phy {
184 compatible = "samsung,s5pv210-mipi-video-phy";
185 #phy-cells = <1>;
189 pd_cam: power-domain@10023c00 {
190 compatible = "samsung,exynos4210-pd";
192 #power-domain-cells = <0>;
196 pd_mfc: power-domain@10023c40 {
197 compatible = "samsung,exynos4210-pd";
199 #power-domain-cells = <0>;
203 pd_g3d: power-domain@10023c60 {
204 compatible = "samsung,exynos4210-pd";
206 #power-domain-cells = <0>;
210 pd_lcd0: power-domain@10023c80 {
211 compatible = "samsung,exynos4210-pd";
213 #power-domain-cells = <0>;
217 pd_isp: power-domain@10023ca0 {
218 compatible = "samsung,exynos4210-pd";
220 #power-domain-cells = <0>;
224 cmu: clock-controller@10030000 {
225 compatible = "samsung,exynos3250-cmu";
227 #clock-cells = <1>;
228 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
234 cmu_dmc: clock-controller@105c0000 {
235 compatible = "samsung,exynos3250-cmu-dmc";
237 #clock-cells = <1>;
241 compatible = "samsung,s3c6410-rtc";
245 interrupt-parent = <&pmu_system_controller>;
250 compatible = "samsung,exynos3250-tmu";
254 clock-names = "tmu_apbif";
255 #thermal-sensor-cells = <0>;
259 gic: interrupt-controller@10481000 {
260 compatible = "arm,cortex-a15-gic";
261 #interrupt-cells = <3>;
262 interrupt-controller;
272 compatible = "samsung,exynos3250-mct",
273 "samsung,exynos4210-mct";
284 clock-names = "fin_pll", "mct";
288 compatible = "samsung,exynos3250-pinctrl";
292 wakeup-interrupt-controller {
293 compatible = "samsung,exynos4210-wakeup-eint";
299 compatible = "samsung,exynos3250-pinctrl";
305 compatible = "samsung,exynos3250-jpeg";
309 clock-names = "jpeg", "sclk";
310 power-domains = <&pd_cam>;
311 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
312 assigned-clock-rates = <0>, <150000000>;
313 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
319 compatible = "samsung,exynos-sysmmu";
322 clock-names = "sysmmu", "master";
324 power-domains = <&pd_cam>;
325 #iommu-cells = <0>;
329 compatible = "samsung,exynos3250-fimd";
331 interrupt-names = "fifo", "vsync", "lcd_sys";
336 clock-names = "sclk_fimd", "fimd";
337 power-domains = <&pd_lcd0>;
344 compatible = "samsung,exynos3250-mipi-dsi";
347 samsung,phy-type = <0>;
348 power-domains = <&pd_lcd0>;
350 phy-names = "dsim";
352 clock-names = "bus_clk", "pll_clk";
353 #address-cells = <1>;
354 #size-cells = <0>;
359 compatible = "samsung,exynos-sysmmu";
362 clock-names = "sysmmu", "master";
364 power-domains = <&pd_lcd0>;
365 #iommu-cells = <0>;
369 compatible = "samsung,s3c6400-hsotg";
373 clock-names = "otg";
375 phy-names = "usb2-phy";
380 compatible = "samsung,exynos5420-dw-mshc";
384 clock-names = "biu", "ciu";
385 fifo-depth = <0x80>;
386 #address-cells = <1>;
387 #size-cells = <0>;
392 compatible = "samsung,exynos5420-dw-mshc";
396 clock-names = "biu", "ciu";
397 fifo-depth = <0x80>;
398 #address-cells = <1>;
399 #size-cells = <0>;
404 compatible = "samsung,exynos5250-dw-mshc";
408 clock-names = "biu", "ciu";
409 fifo-depth = <0x80>;
410 #address-cells = <1>;
411 #size-cells = <0>;
415 exynos_usbphy: exynos-usbphy@125b0000 {
416 compatible = "samsung,exynos3250-usb2-phy";
418 samsung,pmureg-phandle = <&pmu_system_controller>;
420 clock-names = "phy", "ref";
421 #phy-cells = <1>;
425 pdma0: dma-controller@12680000 {
430 clock-names = "apb_pclk";
431 #dma-cells = <1>;
434 pdma1: dma-controller@12690000 {
439 clock-names = "apb_pclk";
440 #dma-cells = <1>;
444 compatible = "samsung,exynos3250-adc";
447 clock-names = "adc", "sclk";
449 #io-channel-cells = <1>;
450 samsung,syscon-phandle = <&pmu_system_controller>;
455 compatible = "samsung,exynos4210-mali", "arm,mali-400";
468 interrupt-names = "gp",
481 clock-names = "bus", "core";
482 power-domains = <&pd_g3d>;
488 compatible = "samsung,mfc-v7";
491 clock-names = "mfc", "sclk_mfc";
493 power-domains = <&pd_mfc>;
498 compatible = "samsung,exynos-sysmmu";
501 clock-names = "sysmmu", "master";
503 power-domains = <&pd_mfc>;
504 #iommu-cells = <0>;
508 compatible = "samsung,exynos4210-uart";
512 clock-names = "uart", "clk_uart_baud0";
513 pinctrl-names = "default";
514 pinctrl-0 = <&uart0_data &uart0_fctl>;
519 compatible = "samsung,exynos4210-uart";
523 clock-names = "uart", "clk_uart_baud0";
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart1_data>;
530 compatible = "samsung,exynos4210-uart";
534 clock-names = "uart", "clk_uart_baud0";
535 pinctrl-names = "default";
536 pinctrl-0 = <&uart2_data>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "samsung,s3c2440-i2c";
547 clock-names = "i2c";
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c0_bus>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "samsung,s3c2440-i2c";
560 clock-names = "i2c";
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c1_bus>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 compatible = "samsung,s3c2440-i2c";
573 clock-names = "i2c";
574 pinctrl-names = "default";
575 pinctrl-0 = <&i2c2_bus>;
580 #address-cells = <1>;
581 #size-cells = <0>;
582 compatible = "samsung,s3c2440-i2c";
586 clock-names = "i2c";
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c3_bus>;
593 #address-cells = <1>;
594 #size-cells = <0>;
595 compatible = "samsung,s3c2440-i2c";
599 clock-names = "i2c";
600 pinctrl-names = "default";
601 pinctrl-0 = <&i2c4_bus>;
606 #address-cells = <1>;
607 #size-cells = <0>;
608 compatible = "samsung,s3c2440-i2c";
612 clock-names = "i2c";
613 pinctrl-names = "default";
614 pinctrl-0 = <&i2c5_bus>;
619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "samsung,s3c2440-i2c";
625 clock-names = "i2c";
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c6_bus>;
632 #address-cells = <1>;
633 #size-cells = <0>;
634 compatible = "samsung,s3c2440-i2c";
638 clock-names = "i2c";
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2c7_bus>;
645 compatible = "samsung,exynos4210-spi";
649 dma-names = "tx", "rx";
650 #address-cells = <1>;
651 #size-cells = <0>;
653 clock-names = "spi", "spi_busclk0";
654 samsung,spi-src-clk = <0>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi0_bus>;
661 compatible = "samsung,exynos4210-spi";
665 dma-names = "tx", "rx";
666 #address-cells = <1>;
667 #size-cells = <0>;
669 clock-names = "spi", "spi_busclk0";
670 samsung,spi-src-clk = <0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi1_bus>;
677 compatible = "samsung,s3c6410-i2s";
681 clock-names = "iis", "i2s_opclk0";
683 dma-names = "tx", "rx";
684 pinctrl-0 = <&i2s2_bus>;
685 pinctrl-names = "default";
690 compatible = "samsung,exynos4210-pwm";
697 #pwm-cells = <3>;
702 compatible = "samsung,exynos-ppmu";
708 compatible = "samsung,exynos-ppmu";
714 compatible = "samsung,exynos-ppmu";
720 compatible = "samsung,exynos-ppmu";
723 clock-names = "ppmu";
728 compatible = "samsung,exynos-ppmu";
731 clock-names = "ppmu";
736 compatible = "samsung,exynos-ppmu";
739 clock-names = "ppmu";
744 compatible = "samsung,exynos-ppmu";
747 clock-names = "ppmu";
752 compatible = "samsung,exynos-ppmu";
755 clock-names = "ppmu";
760 compatible = "samsung,exynos-ppmu";
763 clock-names = "ppmu";
768 compatible = "samsung,exynos-ppmu";
771 clock-names = "ppmu";
775 bus_dmc: bus-dmc {
776 compatible = "samsung,exynos-bus";
778 clock-names = "bus";
779 operating-points-v2 = <&bus_dmc_opp_table>;
783 bus_dmc_opp_table: opp-table1 {
784 compatible = "operating-points-v2";
786 opp-50000000 {
787 opp-hz = /bits/ 64 <50000000>;
788 opp-microvolt = <800000>;
790 opp-100000000 {
791 opp-hz = /bits/ 64 <100000000>;
792 opp-microvolt = <800000>;
794 opp-134000000 {
795 opp-hz = /bits/ 64 <134000000>;
796 opp-microvolt = <800000>;
798 opp-200000000 {
799 opp-hz = /bits/ 64 <200000000>;
800 opp-microvolt = <825000>;
802 opp-400000000 {
803 opp-hz = /bits/ 64 <400000000>;
804 opp-microvolt = <875000>;
808 bus_leftbus: bus-leftbus {
809 compatible = "samsung,exynos-bus";
811 clock-names = "bus";
812 operating-points-v2 = <&bus_leftbus_opp_table>;
816 bus_rightbus: bus-rightbus {
817 compatible = "samsung,exynos-bus";
819 clock-names = "bus";
820 operating-points-v2 = <&bus_leftbus_opp_table>;
824 bus_lcd0: bus-lcd0 {
825 compatible = "samsung,exynos-bus";
827 clock-names = "bus";
828 operating-points-v2 = <&bus_leftbus_opp_table>;
832 bus_fsys: bus-fsys {
833 compatible = "samsung,exynos-bus";
835 clock-names = "bus";
836 operating-points-v2 = <&bus_leftbus_opp_table>;
840 bus_mcuisp: bus-mcuisp {
841 compatible = "samsung,exynos-bus";
843 clock-names = "bus";
844 operating-points-v2 = <&bus_mcuisp_opp_table>;
848 bus_isp: bus-isp {
849 compatible = "samsung,exynos-bus";
851 clock-names = "bus";
852 operating-points-v2 = <&bus_isp_opp_table>;
856 bus_peril: bus-peril {
857 compatible = "samsung,exynos-bus";
859 clock-names = "bus";
860 operating-points-v2 = <&bus_peril_opp_table>;
864 bus_mfc: bus-mfc {
865 compatible = "samsung,exynos-bus";
867 clock-names = "bus";
868 operating-points-v2 = <&bus_leftbus_opp_table>;
872 bus_leftbus_opp_table: opp-table2 {
873 compatible = "operating-points-v2";
875 opp-50000000 {
876 opp-hz = /bits/ 64 <50000000>;
877 opp-microvolt = <900000>;
879 opp-80000000 {
880 opp-hz = /bits/ 64 <80000000>;
881 opp-microvolt = <900000>;
883 opp-100000000 {
884 opp-hz = /bits/ 64 <100000000>;
885 opp-microvolt = <1000000>;
887 opp-134000000 {
888 opp-hz = /bits/ 64 <134000000>;
889 opp-microvolt = <1000000>;
891 opp-200000000 {
892 opp-hz = /bits/ 64 <200000000>;
893 opp-microvolt = <1000000>;
897 bus_mcuisp_opp_table: opp-table3 {
898 compatible = "operating-points-v2";
900 opp-50000000 {
901 opp-hz = /bits/ 64 <50000000>;
903 opp-80000000 {
904 opp-hz = /bits/ 64 <80000000>;
906 opp-100000000 {
907 opp-hz = /bits/ 64 <100000000>;
909 opp-200000000 {
910 opp-hz = /bits/ 64 <200000000>;
912 opp-400000000 {
913 opp-hz = /bits/ 64 <400000000>;
917 bus_isp_opp_table: opp-table4 {
918 compatible = "operating-points-v2";
920 opp-50000000 {
921 opp-hz = /bits/ 64 <50000000>;
923 opp-80000000 {
924 opp-hz = /bits/ 64 <80000000>;
926 opp-100000000 {
927 opp-hz = /bits/ 64 <100000000>;
929 opp-200000000 {
930 opp-hz = /bits/ 64 <200000000>;
932 opp-300000000 {
933 opp-hz = /bits/ 64 <300000000>;
937 bus_peril_opp_table: opp-table5 {
938 compatible = "operating-points-v2";
940 opp-50000000 {
941 opp-hz = /bits/ 64 <50000000>;
943 opp-80000000 {
944 opp-hz = /bits/ 64 <80000000>;
946 opp-100000000 {
947 opp-hz = /bits/ 64 <100000000>;
953 #include "exynos3250-pinctrl.dtsi"
954 #include "exynos-syscon-restart.dtsi"