Lines Matching +full:0 +full:x10030000
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0>;
111 xusbxti: clock-0 {
113 clock-frequency = <0>;
114 #clock-cells = <0>;
120 clock-frequency = <0>;
121 #clock-cells = <0>;
127 clock-frequency = <0>;
128 #clock-cells = <0>;
146 reg = <0x02020000 0x40000>;
149 ranges = <0 0x02020000 0x40000>;
151 smp-sram@0 {
153 reg = <0x0 0x1000>;
158 reg = <0x3f000 0x1000>;
164 reg = <0x10000000 0x100>;
169 reg = <0x10010000 0x400>;
174 reg = <0x10020000 0x4000>;
191 reg = <0x10023C00 0x20>;
192 #power-domain-cells = <0>;
198 reg = <0x10023C40 0x20>;
199 #power-domain-cells = <0>;
205 reg = <0x10023C60 0x20>;
206 #power-domain-cells = <0>;
212 reg = <0x10023C80 0x20>;
213 #power-domain-cells = <0>;
219 reg = <0x10023CA0 0x20>;
220 #power-domain-cells = <0>;
226 reg = <0x10030000 0x20000>;
236 reg = <0x105C0000 0x2000>;
242 reg = <0x10070000 0x100>;
251 reg = <0x100C0000 0x100>;
255 #thermal-sensor-cells = <0>;
263 reg = <0x10481000 0x1000>,
264 <0x10482000 0x2000>,
265 <0x10484000 0x2000>,
266 <0x10486000 0x2000>;
274 reg = <0x10050000 0x800>;
289 reg = <0x11000000 0x1000>;
300 reg = <0x11400000 0x1000>;
306 reg = <0x11830000 0x1000>;
312 assigned-clock-rates = <0>, <150000000>;
320 reg = <0x11a60000 0x1000>;
325 #iommu-cells = <0>;
330 reg = <0x11c00000 0x30000>;
345 reg = <0x11C80000 0x10000>;
347 samsung,phy-type = <0>;
354 #size-cells = <0>;
360 reg = <0x11e20000 0x1000>;
365 #iommu-cells = <0>;
370 reg = <0x12480000 0x20000>;
374 phys = <&exynos_usbphy 0>;
381 reg = <0x12510000 0x1000>;
385 fifo-depth = <0x80>;
387 #size-cells = <0>;
393 reg = <0x12520000 0x1000>;
397 fifo-depth = <0x80>;
399 #size-cells = <0>;
405 reg = <0x12530000 0x1000>;
409 fifo-depth = <0x80>;
411 #size-cells = <0>;
417 reg = <0x125B0000 0x100>;
427 reg = <0x12680000 0x1000>;
436 reg = <0x12690000 0x1000>;
445 reg = <0x126C0000 0x100>;
456 reg = <0x13000000 0x10000>;
489 reg = <0x13400000 0x10000>;
499 reg = <0x13620000 0x1000>;
504 #iommu-cells = <0>;
509 reg = <0x13800000 0x100>;
514 pinctrl-0 = <&uart0_data &uart0_fctl>;
520 reg = <0x13810000 0x100>;
525 pinctrl-0 = <&uart1_data>;
531 reg = <0x13820000 0x100>;
536 pinctrl-0 = <&uart2_data>;
542 #size-cells = <0>;
544 reg = <0x13860000 0x100>;
549 pinctrl-0 = <&i2c0_bus>;
555 #size-cells = <0>;
557 reg = <0x13870000 0x100>;
562 pinctrl-0 = <&i2c1_bus>;
568 #size-cells = <0>;
570 reg = <0x13880000 0x100>;
575 pinctrl-0 = <&i2c2_bus>;
581 #size-cells = <0>;
583 reg = <0x13890000 0x100>;
588 pinctrl-0 = <&i2c3_bus>;
594 #size-cells = <0>;
596 reg = <0x138A0000 0x100>;
601 pinctrl-0 = <&i2c4_bus>;
607 #size-cells = <0>;
609 reg = <0x138B0000 0x100>;
614 pinctrl-0 = <&i2c5_bus>;
620 #size-cells = <0>;
622 reg = <0x138C0000 0x100>;
627 pinctrl-0 = <&i2c6_bus>;
633 #size-cells = <0>;
635 reg = <0x138D0000 0x100>;
640 pinctrl-0 = <&i2c7_bus>;
646 reg = <0x13920000 0x100>;
651 #size-cells = <0>;
654 samsung,spi-src-clk = <0>;
656 pinctrl-0 = <&spi0_bus>;
662 reg = <0x13930000 0x100>;
667 #size-cells = <0>;
670 samsung,spi-src-clk = <0>;
672 pinctrl-0 = <&spi1_bus>;
678 reg = <0x13970000 0x100>;
684 pinctrl-0 = <&i2s2_bus>;
691 reg = <0x139D0000 0x1000>;
703 reg = <0x106a0000 0x2000>;
709 reg = <0x106b0000 0x2000>;
715 reg = <0x106c0000 0x2000>;
721 reg = <0x112a0000 0x2000>;
729 reg = <0x116a0000 0x2000>;
737 reg = <0x11ac0000 0x2000>;
745 reg = <0x11e40000 0x2000>;
753 reg = <0x12630000 0x2000>;
761 reg = <0x13220000 0x2000>;
769 reg = <0x13660000 0x2000>;