Lines Matching +full:omap5 +full:- +full:ipu
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
48 compatible = "arm,armv7-timer";
54 interrupt-parent = <&gic>;
57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller;
60 #interrupt-cells = <3>;
66 interrupt-parent = <&gic>;
69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 interrupt-controller;
72 #interrupt-cells = <3>;
74 interrupt-parent = <&gic>;
78 #address-cells = <1>;
79 #size-cells = <0>;
83 compatible = "arm,cortex-a15";
86 operating-points-v2 = <&cpu0_opp_table>;
89 clock-names = "cpu";
91 clock-latency = <300000>; /* From omap-cpufreq driver */
94 #cooling-cells = <2>; /* min followed by max */
96 vbb-supply = <&abb_mpu>;
100 cpu0_opp_table: opp-table {
101 compatible = "operating-points-v2-ti-cpu";
104 opp_nom-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
108 opp-supported-hw = <0xFF 0x01>;
109 opp-suspend;
112 opp_od-1176000000 {
113 opp-hz = /bits/ 64 <1176000000>;
114 opp-microvolt = <1160000 885000 1160000>,
117 opp-supported-hw = <0xFF 0x02>;
121 opp-hz = /bits/ 64 <1500000000>;
122 opp-microvolt = <1210000 950000 1250000>,
124 opp-supported-hw = <0xFF 0x04>;
136 compatible = "simple-pm-bus";
137 power-domains = <&prm_core>;
140 #address-cells = <1>;
141 #size-cells = <1>;
143 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
145 l3-noc@44000000 {
146 compatible = "ti,dra7-l3-noc";
149 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
160 target-module@48210000 {
161 compatible = "ti,sysc-omap4-simple", "ti,sysc";
162 power-domains = <&prm_mpu>;
164 clock-names = "fck";
165 #address-cells = <1>;
166 #size-cells = <1>;
170 compatible = "ti,omap5-mpu";
182 * 26-678. Main Sequence PCIe Controller Global Initialization"
185 axi0: target-module@51000000 {
186 compatible = "ti,sysc-omap4", "ti,sysc";
187 power-domains = <&prm_l3init>;
189 reset-names = "rstctrl";
193 clock-names = "fck", "phy-clk", "phy-clk-div";
194 #size-cells = <1>;
195 #address-cells = <1>;
198 dma-ranges;
207 reg-names = "rc_dbics", "ti_conf", "config";
209 #address-cells = <3>;
210 #size-cells = <2>;
214 bus-range = <0x00 0xff>;
215 #interrupt-cells = <1>;
216 num-lanes = <1>;
217 linux,pci-domain = <0>;
219 phy-names = "pcie-phy0";
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 interrupt-map-mask = <0 0 0 7>;
222 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
228 pcie1_intc: interrupt-controller {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <1>;
240 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
242 num-lanes = <1>;
243 num-ib-windows = <4>;
244 num-ob-windows = <16>;
246 phy-names = "pcie-phy0";
247 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
248 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
256 * 26-678. Main Sequence PCIe Controller Global Initialization"
259 axi1: target-module@51800000 {
260 compatible = "ti,sysc-omap4", "ti,sysc";
264 clock-names = "fck", "phy-clk", "phy-clk-div";
265 power-domains = <&prm_l3init>;
267 reset-names = "rstctrl";
268 #size-cells = <1>;
269 #address-cells = <1>;
272 dma-ranges;
278 reg-names = "rc_dbics", "ti_conf", "config";
280 #address-cells = <3>;
281 #size-cells = <2>;
285 bus-range = <0x00 0xff>;
286 #interrupt-cells = <1>;
287 num-lanes = <1>;
288 linux,pci-domain = <1>;
290 phy-names = "pcie-phy0";
291 interrupt-map-mask = <0 0 0 7>;
292 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
296 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
297 pcie2_intc: interrupt-controller {
298 interrupt-controller;
299 #address-cells = <0>;
300 #interrupt-cells = <1>;
306 compatible = "mmio-sram";
309 #address-cells = <1>;
310 #size-cells = <1>;
322 sram-hs@0 {
323 compatible = "ti,secure-ram";
336 compatible = "mmio-sram";
339 #address-cells = <1>;
340 #size-cells = <1>;
345 compatible = "mmio-sram";
348 #address-cells = <1>;
349 #size-cells = <1>;
359 compatible = "ti,dra752-bandgap";
361 #thermal-sensor-cells = <1>;
370 compatible = "ti,dra7-iodelay";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 #pinctrl-cells = <2>;
377 target-module@43300000 {
378 compatible = "ti,sysc-omap4", "ti,sysc";
381 reg-names = "rev", "sysc";
382 ti,sysc-midle = <SYSC_IDLE_FORCE>,
385 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
389 clock-names = "fck";
390 #address-cells = <1>;
391 #size-cells = <1>;
395 compatible = "ti,edma3-tpcc";
397 reg-names = "edma3_cc";
401 interrupt-names = "edma3_ccint", "edma3_mperr",
403 dma-requests = <64>;
404 #dma-cells = <2>;
410 * ti,edma-memcpy-channels = <20 21>;
417 target-module@43400000 {
418 compatible = "ti,sysc-omap4", "ti,sysc";
421 reg-names = "rev", "sysc";
422 ti,sysc-midle = <SYSC_IDLE_FORCE>,
425 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
429 clock-names = "fck";
430 #address-cells = <1>;
431 #size-cells = <1>;
435 compatible = "ti,edma3-tptc";
438 interrupt-names = "edma3_tcerrint";
442 target-module@43500000 {
443 compatible = "ti,sysc-omap4", "ti,sysc";
446 reg-names = "rev", "sysc";
447 ti,sysc-midle = <SYSC_IDLE_FORCE>,
450 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
454 clock-names = "fck";
455 #address-cells = <1>;
456 #size-cells = <1>;
460 compatible = "ti,edma3-tptc";
463 interrupt-names = "edma3_tcerrint";
467 target-module@4e000000 {
468 compatible = "ti,sysc-omap2", "ti,sysc";
471 reg-names = "rev", "sysc";
472 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
476 #size-cells = <1>;
477 #address-cells = <1>;
480 compatible = "ti,omap5-dmm";
486 ipu1: ipu@58820000 {
487 compatible = "ti,dra7-ipu";
489 reg-names = "l2ram";
494 firmware-name = "dra7-ipu1-fw.xem4";
497 ipu2: ipu@55020000 {
498 compatible = "ti,dra7-ipu";
500 reg-names = "l2ram";
505 firmware-name = "dra7-ipu2-fw.xem4";
509 compatible = "ti,dra7-dsp";
513 reg-names = "l2ram", "l1pram", "l1dram";
519 firmware-name = "dra7-dsp1-fw.xe66";
522 target-module@40d01000 {
523 compatible = "ti,sysc-omap2", "ti,sysc";
527 reg-names = "rev", "sysc", "syss";
528 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
531 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
535 clock-names = "fck";
537 reset-names = "rstctrl";
539 #size-cells = <1>;
540 #address-cells = <1>;
543 compatible = "ti,dra7-dsp-iommu";
546 #iommu-cells = <0>;
547 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
551 target-module@40d02000 {
552 compatible = "ti,sysc-omap2", "ti,sysc";
556 reg-names = "rev", "sysc", "syss";
557 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
560 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
564 clock-names = "fck";
566 reset-names = "rstctrl";
568 #size-cells = <1>;
569 #address-cells = <1>;
572 compatible = "ti,dra7-dsp-iommu";
575 #iommu-cells = <0>;
576 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
580 target-module@58882000 {
581 compatible = "ti,sysc-omap2", "ti,sysc";
585 reg-names = "rev", "sysc", "syss";
586 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
589 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
593 clock-names = "fck";
595 reset-names = "rstctrl";
596 #address-cells = <1>;
597 #size-cells = <1>;
601 compatible = "ti,dra7-iommu";
604 #iommu-cells = <0>;
605 ti,iommu-bus-err-back;
609 target-module@55082000 {
610 compatible = "ti,sysc-omap2", "ti,sysc";
614 reg-names = "rev", "sysc", "syss";
615 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
618 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
622 clock-names = "fck";
624 reset-names = "rstctrl";
625 #address-cells = <1>;
626 #size-cells = <1>;
630 compatible = "ti,dra7-iommu";
633 #iommu-cells = <0>;
634 ti,iommu-bus-err-back;
638 abb_mpu: regulator-abb-mpu {
639 compatible = "ti,abb-v3";
640 regulator-name = "abb_mpu";
641 #address-cells = <0>;
642 #size-cells = <0>;
644 ti,settling-time = <50>;
645 ti,clock-cycles = <16>;
650 reg-names = "setup-address", "control-address",
651 "int-address", "efuse-address",
652 "ldo-address";
653 ti,tranxdone-status-mask = <0x80>;
655 ti,ldovbb-override-mask = <0x400>;
657 ti,ldovbb-vset-mask = <0x1F>;
671 abb_ivahd: regulator-abb-ivahd {
672 compatible = "ti,abb-v3";
673 regulator-name = "abb_ivahd";
674 #address-cells = <0>;
675 #size-cells = <0>;
677 ti,settling-time = <50>;
678 ti,clock-cycles = <16>;
683 reg-names = "setup-address", "control-address",
684 "int-address", "efuse-address",
685 "ldo-address";
686 ti,tranxdone-status-mask = <0x40000000>;
688 ti,ldovbb-override-mask = <0x400>;
690 ti,ldovbb-vset-mask = <0x1F>;
704 abb_dspeve: regulator-abb-dspeve {
705 compatible = "ti,abb-v3";
706 regulator-name = "abb_dspeve";
707 #address-cells = <0>;
708 #size-cells = <0>;
710 ti,settling-time = <50>;
711 ti,clock-cycles = <16>;
716 reg-names = "setup-address", "control-address",
717 "int-address", "efuse-address",
718 "ldo-address";
719 ti,tranxdone-status-mask = <0x20000000>;
721 ti,ldovbb-override-mask = <0x400>;
723 ti,ldovbb-vset-mask = <0x1F>;
737 abb_gpu: regulator-abb-gpu {
738 compatible = "ti,abb-v3";
739 regulator-name = "abb_gpu";
740 #address-cells = <0>;
741 #size-cells = <0>;
743 ti,settling-time = <50>;
744 ti,clock-cycles = <16>;
749 reg-names = "setup-address", "control-address",
750 "int-address", "efuse-address",
751 "ldo-address";
752 ti,tranxdone-status-mask = <0x10000000>;
754 ti,ldovbb-override-mask = <0x400>;
756 ti,ldovbb-vset-mask = <0x1F>;
770 target-module@4b300000 {
771 compatible = "ti,sysc-omap4", "ti,sysc";
774 reg-names = "rev", "sysc";
775 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
780 clock-names = "fck";
781 #address-cells = <1>;
782 #size-cells = <1>;
787 compatible = "ti,dra7xxx-qspi";
790 reg-names = "qspi_base", "qspi_mmap";
791 syscon-chipselects = <&scm_conf 0x558>;
792 #address-cells = <1>;
793 #size-cells = <0>;
795 clock-names = "fck";
796 num-cs = <4>;
805 target-module@50000000 {
806 compatible = "ti,sysc-omap2", "ti,sysc";
810 reg-names = "rev", "sysc", "syss";
811 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
814 ti,syss-mask = <1>;
816 clock-names = "fck";
817 #address-cells = <1>;
818 #size-cells = <1>;
823 compatible = "ti,am3352-gpmc";
827 dma-names = "rxtx";
828 gpmc,num-cs = <8>;
829 gpmc,num-waitpins = <2>;
830 #address-cells = <2>;
831 #size-cells = <1>;
832 interrupt-controller;
833 #interrupt-cells = <2>;
834 gpio-controller;
835 #gpio-cells = <2>;
840 target-module@56000000 {
841 compatible = "ti,sysc-omap4", "ti,sysc";
844 reg-names = "rev", "sysc";
845 ti,sysc-midle = <SYSC_IDLE_FORCE>,
848 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
852 clock-names = "fck";
853 #address-cells = <1>;
854 #size-cells = <1>;
859 compatible = "ti,irq-crossbar";
861 interrupt-controller;
862 interrupt-parent = <&wakeupgen>;
863 #interrupt-cells = <3>;
864 ti,max-irqs = <160>;
865 ti,max-crossbar-sources = <MAX_SOURCES>;
866 ti,reg-size = <2>;
867 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
868 ti,irqs-skip = <10 133 139 140>;
869 ti,irqs-safe-map = <0>;
872 target-module@58000000 {
873 compatible = "ti,sysc-omap2", "ti,sysc";
876 reg-names = "rev", "syss";
877 ti,syss-mask = <1>;
882 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
883 #address-cells = <1>;
884 #size-cells = <1>;
888 compatible = "ti,dra7-dss";
893 syscon-pll-ctrl = <&scm_conf 0x538>;
894 #address-cells = <1>;
895 #size-cells = <1>;
898 target-module@1000 {
899 compatible = "ti,sysc-omap2", "ti,sysc";
903 reg-names = "rev", "sysc", "syss";
904 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
907 ti,sysc-midle = <SYSC_IDLE_FORCE>,
910 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
914 ti,syss-mask = <1>;
916 clock-names = "fck";
917 #address-cells = <1>;
918 #size-cells = <1>;
922 compatible = "ti,dra7-dispc";
926 clock-names = "fck";
928 syscon-pol = <&scm_conf 0x534>;
932 target-module@40000 {
933 compatible = "ti,sysc-omap4", "ti,sysc";
936 reg-names = "rev", "sysc";
937 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
941 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
944 clock-names = "fck", "dss_clk";
945 #address-cells = <1>;
946 #size-cells = <1>;
950 compatible = "ti,dra7-hdmi";
955 reg-names = "wp", "pll", "phy", "core";
960 clock-names = "fck", "sys_clk";
962 dma-names = "audio_tx";
968 target-module@59000000 {
969 compatible = "ti,sysc-omap4", "ti,sysc";
971 reg-names = "rev";
973 clock-names = "fck";
974 #address-cells = <1>;
975 #size-cells = <1>;
983 clock-names = "core";
987 aes1_target: target-module@4b500000 {
988 compatible = "ti,sysc-omap2", "ti,sysc";
992 reg-names = "rev", "sysc", "syss";
993 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
995 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
999 ti,syss-mask = <1>;
1002 clock-names = "fck";
1003 #address-cells = <1>;
1004 #size-cells = <1>;
1008 compatible = "ti,omap4-aes";
1012 dma-names = "tx", "rx";
1014 clock-names = "fck";
1018 aes2_target: target-module@4b700000 {
1019 compatible = "ti,sysc-omap2", "ti,sysc";
1023 reg-names = "rev", "sysc", "syss";
1024 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1026 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1030 ti,syss-mask = <1>;
1033 clock-names = "fck";
1034 #address-cells = <1>;
1035 #size-cells = <1>;
1039 compatible = "ti,omap4-aes";
1043 dma-names = "tx", "rx";
1045 clock-names = "fck";
1049 sham1_target: target-module@4b101000 {
1050 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1054 reg-names = "rev", "sysc", "syss";
1055 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1057 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1060 ti,syss-mask = <1>;
1063 clock-names = "fck";
1064 #address-cells = <1>;
1065 #size-cells = <1>;
1069 compatible = "ti,omap5-sham";
1073 dma-names = "rx";
1075 clock-names = "fck";
1079 sham2_target: target-module@42701000 {
1080 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1084 reg-names = "rev", "sysc", "syss";
1085 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1087 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1090 ti,syss-mask = <1>;
1093 clock-names = "fck";
1094 #address-cells = <1>;
1095 #size-cells = <1>;
1099 compatible = "ti,omap5-sham";
1103 dma-names = "rx";
1105 clock-names = "fck";
1109 iva_hd_target: target-module@5a000000 {
1110 compatible = "ti,sysc-omap4", "ti,sysc";
1113 reg-names = "rev", "sysc";
1114 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1117 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1120 power-domains = <&prm_iva>;
1122 reset-names = "rstctrl";
1124 clock-names = "fck";
1125 #address-cells = <1>;
1126 #size-cells = <1>;
1135 opp_supply_mpu: opp-supply@4a003b20 {
1136 compatible = "ti,omap5-opp-supply";
1138 ti,efuse-settings = <
1144 ti,absolute-max-voltage-uv = <1500000>;
1149 thermal_zones: thermal-zones {
1150 #include "omap4-cpu-thermal.dtsi"
1151 #include "omap5-gpu-thermal.dtsi"
1152 #include "omap5-core-thermal.dtsi"
1153 #include "dra7-dspeve-thermal.dtsi"
1154 #include "dra7-iva-thermal.dtsi"
1160 polling-delay = <500>; /* milliseconds */
1200 #include "dra7-l4.dtsi"
1201 #include "dra7xx-clocks.dtsi"
1205 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1207 #power-domain-cells = <0>;
1211 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1213 #reset-cells = <1>;
1214 #power-domain-cells = <0>;
1218 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1220 #reset-cells = <1>;
1221 #power-domain-cells = <0>;
1225 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1227 #power-domain-cells = <0>;
1231 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1233 #reset-cells = <1>;
1234 #power-domain-cells = <0>;
1238 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1240 #reset-cells = <1>;
1241 #power-domain-cells = <0>;
1245 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1247 #power-domain-cells = <0>;
1251 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1253 #power-domain-cells = <0>;
1257 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1259 #power-domain-cells = <0>;
1263 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1265 #reset-cells = <1>;
1266 #power-domain-cells = <0>;
1270 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1272 #power-domain-cells = <0>;
1276 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1278 #power-domain-cells = <0>;
1282 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1284 #power-domain-cells = <0>;
1288 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1290 #reset-cells = <1>;
1291 #power-domain-cells = <0>;
1295 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1297 #power-domain-cells = <0>;
1301 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1303 #power-domain-cells = <0>;
1307 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1309 #power-domain-cells = <0>;
1313 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1315 #power-domain-cells = <0>;
1319 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1321 #power-domain-cells = <0>;
1325 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1327 #power-domain-cells = <0>;
1331 /* Preferred always-on timer for clockevent */
1333 ti,no-reset-on-init;
1334 ti,no-idle;
1336 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1337 assigned-clock-parents = <&sys_32k_ck>;
1343 ti,no-reset-on-init;
1344 ti,no-idle;
1346 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1347 assigned-clock-parents = <&timer_sys_clk_div>;
1352 ti,no-reset-on-init;
1353 ti,no-idle;
1355 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1356 assigned-clock-parents = <&timer_sys_clk_div>;