Lines Matching +full:0 +full:x40800000
61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
117 opp-supported-hw = <0xFF 0x02>;
124 opp-supported-hw = <0xFF 0x04>;
138 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
139 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
142 ranges = <0x0 0x0 0x0 0xc0000000>;
143 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 reg = <0x44000000 0x1000>,
148 <0x45000000 0x1000>;
163 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
167 ranges = <0 0x48210000 0x1f0000>;
188 resets = <&prm_l3init 0>;
190 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
196 ranges = <0x51000000 0x51000000 0x3000>,
197 <0x20000000 0x20000000 0x10000000>;
204 reg = <0x51000000 0x2000>,
205 <0x51002000 0x14c>,
206 <0x20001000 0x2000>;
208 interrupts = <0 232 0x4>, <0 233 0x4>;
212 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
213 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
214 bus-range = <0x00 0xff>;
217 linux,pci-domain = <0>;
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 interrupt-map-mask = <0 0 0 7>;
222 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
223 <0 0 0 2 &pcie1_intc 2>,
224 <0 0 0 3 &pcie1_intc 3>,
225 <0 0 0 4 &pcie1_intc 4>;
226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
230 #address-cells = <0>;
236 reg = <0x51000000 0x28>,
237 <0x51002000 0x14c>,
238 <0x51001000 0x28>,
239 <0x20001000 0x10000000>;
241 interrupts = <0 232 0x4>;
247 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
248 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
261 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
270 ranges = <0x51800000 0x51800000 0x3000>,
271 <0x30000000 0x30000000 0x10000000>;
275 reg = <0x51800000 0x2000>,
276 <0x51802000 0x14c>,
277 <0x30001000 0x2000>;
279 interrupts = <0 355 0x4>, <0 356 0x4>;
283 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
284 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
285 bus-range = <0x00 0xff>;
291 interrupt-map-mask = <0 0 0 7>;
292 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
293 <0 0 0 2 &pcie2_intc 2>,
294 <0 0 0 3 &pcie2_intc 3>,
295 <0 0 0 4 &pcie2_intc 4>;
296 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
299 #address-cells = <0>;
307 reg = <0x40300000 0x80000>;
308 ranges = <0x0 0x40300000 0x80000>;
322 sram-hs@0 {
324 reg = <0x0 0x0>;
337 reg = <0x40400000 0x100000>;
338 ranges = <0x0 0x40400000 0x100000>;
346 reg = <0x40500000 0x100000>;
347 ranges = <0x0 0x40500000 0x100000>;
353 reg = <0x4a0021e0 0xc
354 0x4a00232c 0xc
355 0x4a002380 0x2c
356 0x4a0023C0 0x3c
357 0x4a002564 0x8
358 0x4a002574 0x50>;
366 reg = <0x40d00000 0x100>;
371 reg = <0x4844a000 0x0d1c>;
373 #size-cells = <0>;
379 reg = <0x43300000 0x4>,
380 <0x43300010 0x4>;
388 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
392 ranges = <0x0 0x43300000 0x100000>;
394 edma: dma@0 {
396 reg = <0 0x100000>;
406 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
419 reg = <0x43400000 0x4>,
420 <0x43400010 0x4>;
428 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
432 ranges = <0x0 0x43400000 0x100000>;
434 edma_tptc0: dma@0 {
436 reg = <0 0x100000>;
444 reg = <0x43500000 0x4>,
445 <0x43500010 0x4>;
453 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
457 ranges = <0x0 0x43500000 0x100000>;
459 edma_tptc1: dma@0 {
461 reg = <0 0x100000>;
469 reg = <0x4e000000 0x4>,
470 <0x4e000010 0x4>;
475 ranges = <0x0 0x4e000000 0x2000000>;
479 dmm@0 {
481 reg = <0 0x800>;
488 reg = <0x58820000 0x10000>;
492 resets = <&prm_ipu 0>, <&prm_ipu 1>;
493 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
499 reg = <0x55020000 0x10000>;
503 resets = <&prm_core 0>, <&prm_core 1>;
504 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
510 reg = <0x40800000 0x48000>,
511 <0x40e00000 0x8000>,
512 <0x40f00000 0x8000>;
514 ti,bootreg = <&scm_conf 0x55c 10>;
517 resets = <&prm_dsp1 0>;
518 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
524 reg = <0x40d01000 0x4>,
525 <0x40d01010 0x4>,
526 <0x40d01014 0x4>;
534 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
538 ranges = <0x0 0x40d01000 0x1000>;
542 mmu0_dsp1: mmu@0 {
544 reg = <0x0 0x100>;
546 #iommu-cells = <0>;
547 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
553 reg = <0x40d02000 0x4>,
554 <0x40d02010 0x4>,
555 <0x40d02014 0x4>;
563 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
567 ranges = <0x0 0x40d02000 0x1000>;
571 mmu1_dsp1: mmu@0 {
573 reg = <0x0 0x100>;
575 #iommu-cells = <0>;
576 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
582 reg = <0x58882000 0x4>,
583 <0x58882010 0x4>,
584 <0x58882014 0x4>;
592 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
598 ranges = <0x0 0x58882000 0x100>;
600 mmu_ipu1: mmu@0 {
602 reg = <0x0 0x100>;
604 #iommu-cells = <0>;
611 reg = <0x55082000 0x4>,
612 <0x55082010 0x4>,
613 <0x55082014 0x4>;
621 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
627 ranges = <0x0 0x55082000 0x100>;
629 mmu_ipu2: mmu@0 {
631 reg = <0x0 0x100>;
633 #iommu-cells = <0>;
641 #address-cells = <0>;
642 #size-cells = <0>;
647 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
648 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
649 <0x4ae0c158 0x4>;
653 ti,tranxdone-status-mask = <0x80>;
655 ti,ldovbb-override-mask = <0x400>;
657 ti,ldovbb-vset-mask = <0x1F>;
665 1060000 0 0x0 0 0x02000000 0x01F00000
666 1160000 0 0x4 0 0x02000000 0x01F00000
667 1210000 0 0x8 0 0x02000000 0x01F00000
674 #address-cells = <0>;
675 #size-cells = <0>;
680 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
681 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
682 <0x4a002470 0x4>;
686 ti,tranxdone-status-mask = <0x40000000>;
688 ti,ldovbb-override-mask = <0x400>;
690 ti,ldovbb-vset-mask = <0x1F>;
698 1055000 0 0x0 0 0x02000000 0x01F00000
699 1150000 0 0x4 0 0x02000000 0x01F00000
700 1250000 0 0x8 0 0x02000000 0x01F00000
707 #address-cells = <0>;
708 #size-cells = <0>;
713 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
714 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
715 <0x4a00246c 0x4>;
719 ti,tranxdone-status-mask = <0x20000000>;
721 ti,ldovbb-override-mask = <0x400>;
723 ti,ldovbb-vset-mask = <0x1F>;
731 1055000 0 0x0 0 0x02000000 0x01F00000
732 1150000 0 0x4 0 0x02000000 0x01F00000
733 1250000 0 0x8 0 0x02000000 0x01F00000
740 #address-cells = <0>;
741 #size-cells = <0>;
746 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
747 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
748 <0x4ae0c154 0x4>;
752 ti,tranxdone-status-mask = <0x10000000>;
754 ti,ldovbb-override-mask = <0x400>;
756 ti,ldovbb-vset-mask = <0x1F>;
764 1090000 0 0x0 0 0x02000000 0x01F00000
765 1210000 0 0x4 0 0x02000000 0x01F00000
766 1280000 0 0x8 0 0x02000000 0x01F00000
772 reg = <0x4b300000 0x4>,
773 <0x4b300010 0x4>;
779 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
783 ranges = <0x0 0x4b300000 0x1000>,
784 <0x5c000000 0x5c000000 0x4000000>;
786 qspi: spi@0 {
788 reg = <0 0x100>,
789 <0x5c000000 0x4000000>;
791 syscon-chipselects = <&scm_conf 0x558>;
793 #size-cells = <0>;
807 reg = <0x50000000 4>,
808 <0x50000010 4>,
809 <0x50000014 4>;
815 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
819 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
820 <0x00000000 0x00000000 0x40000000>; /* data */
824 reg = <0x50000000 0x37c>; /* device IO registers */
826 dmas = <&edma_xbar 4 0>;
842 reg = <0x5600fe00 0x4>,
843 <0x5600fe10 0x4>;
851 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
855 ranges = <0 0x56000000 0x2000000>;
860 reg = <0x4a002a48 0x130>;
867 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
869 ti,irqs-safe-map = <0>;
874 reg = <0x58000000 4>,
875 <0x58000014 4>;
878 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
885 ranges = <0 0x58000000 0x800000>;
887 dss: dss@0 {
893 syscon-pll-ctrl = <&scm_conf 0x538>;
896 ranges = <0 0 0x800000>;
900 reg = <0x1000 0x4>,
901 <0x1010 0x4>,
902 <0x1014 0x4>;
919 ranges = <0 0x1000 0x1000>;
921 dispc@0 {
923 reg = <0 0x1000>;
928 syscon-pol = <&scm_conf 0x534>;
934 reg = <0x40000 0x4>,
935 <0x40010 0x4>;
947 ranges = <0 0x40000 0x40000>;
949 hdmi: encoder@0 {
951 reg = <0 0x200>,
952 <0x200 0x80>,
953 <0x300 0x80>,
954 <0x20000 0x19000>;
970 reg = <0x59000020 0x4>;
972 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
976 ranges = <0x0 0x59000000 0x1000>;
978 bb2d: gpu@0 {
980 reg = <0x0 0x700>;
982 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
989 reg = <0x4b500080 0x4>,
990 <0x4b500084 0x4>,
991 <0x4b500088 0x4>;
1001 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1005 ranges = <0x0 0x4b500000 0x1000>;
1007 aes1: aes@0 {
1009 reg = <0 0xa0>;
1011 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1020 reg = <0x4b700080 0x4>,
1021 <0x4b700084 0x4>,
1022 <0x4b700088 0x4>;
1032 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1036 ranges = <0x0 0x4b700000 0x1000>;
1038 aes2: aes@0 {
1040 reg = <0 0xa0>;
1042 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1051 reg = <0x4b101100 0x4>,
1052 <0x4b101110 0x4>,
1053 <0x4b101114 0x4>;
1062 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1066 ranges = <0x0 0x4b101000 0x1000>;
1068 sham1: sham@0 {
1070 reg = <0 0x300>;
1072 dmas = <&edma_xbar 119 0>;
1081 reg = <0x42701100 0x4>,
1082 <0x42701110 0x4>,
1083 <0x42701114 0x4>;
1092 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1096 ranges = <0x0 0x42701000 0x1000>;
1098 sham2: sham@0 {
1100 reg = <0 0x300>;
1102 dmas = <&edma_xbar 165 0>;
1111 reg = <0x5a05a400 0x4>,
1112 <0x5a05a410 0x4>;
1123 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1127 ranges = <0x5a000000 0x5a000000 0x1000000>,
1128 <0x5b000000 0x5b000000 0x1000000>;
1137 reg = <0x4a003b20 0xc>;
1140 1060000 0x0
1141 1160000 0x4
1142 1210000 0x8
1161 coefficients = <0 2000>;
1165 coefficients = <0 2000>;
1169 coefficients = <0 2000>;
1173 coefficients = <0 2000>;
1177 coefficients = <0 2000>;
1206 reg = <0x300 0x100>;
1207 #power-domain-cells = <0>;
1212 reg = <0x400 0x100>;
1214 #power-domain-cells = <0>;
1219 reg = <0x500 0x100>;
1221 #power-domain-cells = <0>;
1226 reg = <0x628 0xd8>;
1227 #power-domain-cells = <0>;
1232 reg = <0x700 0x100>;
1234 #power-domain-cells = <0>;
1239 reg = <0xf00 0x100>;
1241 #power-domain-cells = <0>;
1246 reg = <0x1000 0x100>;
1247 #power-domain-cells = <0>;
1252 reg = <0x1100 0x100>;
1253 #power-domain-cells = <0>;
1258 reg = <0x1200 0x100>;
1259 #power-domain-cells = <0>;
1264 reg = <0x1300 0x100>;
1266 #power-domain-cells = <0>;
1271 reg = <0x1400 0x100>;
1272 #power-domain-cells = <0>;
1277 reg = <0x1600 0x100>;
1278 #power-domain-cells = <0>;
1283 reg = <0x1724 0x100>;
1284 #power-domain-cells = <0>;
1289 reg = <0x1b00 0x40>;
1291 #power-domain-cells = <0>;
1296 reg = <0x1b40 0x40>;
1297 #power-domain-cells = <0>;
1302 reg = <0x1b80 0x40>;
1303 #power-domain-cells = <0>;
1308 reg = <0x1bc0 0x40>;
1309 #power-domain-cells = <0>;
1314 reg = <0x1c00 0x60>;
1315 #power-domain-cells = <0>;
1320 reg = <0x1c60 0x20>;
1321 #power-domain-cells = <0>;
1326 reg = <0x1c80 0x80>;
1327 #power-domain-cells = <0>;
1335 timer@0 {
1345 timer@0 {
1354 timer@0 {