Lines Matching +full:0 +full:x19000000
24 ranges = <0x00000000 0x18000000 0x00001000>;
30 reg = <0x0300 0x100>;
38 reg = <0x0400 0x100>;
42 pinctrl-0 = <&pinmux_uart1>;
49 ranges = <0x00000000 0x19000000 0x00023000>;
53 a9pll: arm_clk@0 {
54 #clock-cells = <0>;
57 reg = <0x00000 0x1000>;
62 reg = <0x20000 0x100>;
67 reg = <0x20200 0x100>;
74 reg = <0x20600 0x20>;
82 reg = <0x20620 0x20>;
91 #address-cells = <0>;
93 reg = <0x21000 0x1000>,
94 <0x20100 0x100>;
99 reg = <0x22000 0x1000>;
121 #clock-cells = <0>;
127 #clock-cells = <0>;
135 #clock-cells = <0>;
143 #clock-cells = <0>;
153 reg = <0x18000000 0x1000>;
154 ranges = <0x00000000 0x18000000 0x00100000>;
159 interrupt-map-mask = <0x000fffff 0xffff>;
162 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
165 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
179 /* PCIe Controller 0 */
180 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
181 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
188 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
189 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
196 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
197 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
204 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
207 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
209 /* Ethernet Controller 0 */
210 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
213 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
216 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
219 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
222 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
223 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
224 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
225 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
226 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
227 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
228 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
229 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
231 chipcommon: chipcommon@0 {
232 reg = <0x00000000 0x1000>;
241 reg = <0x00012000 0x1000>;
245 reg = <0x00013000 0x1000>;
249 reg = <0x00014000 0x1000>;
253 reg = <0x00021000 0x1000>;
262 #usb-cells = <0>;
265 reg = <0x00021000 0x1000>;
270 #size-cells = <0>;
274 #trigger-source-cells = <0>;
279 #trigger-source-cells = <0>;
284 #usb-cells = <0>;
287 reg = <0x00022000 0x1000>;
291 #size-cells = <0>;
295 #trigger-source-cells = <0>;
300 #trigger-source-cells = <0>;
306 reg = <0x00023000 0x1000>;
315 #usb-cells = <0>;
318 reg = <0x00023000 0x1000>;
324 #size-cells = <0>;
328 #trigger-source-cells = <0>;
334 reg = <0x24000 0x800>;
338 reg = <0x25000 0x800>;
342 reg = <0x26000 0x800>;
346 reg = <0x27000 0x800>;
352 reg = <0x18002000 0x28>;
360 reg = <0x18003000 0x8>;
361 #size-cells = <0>;
369 #size-cells = <0>;
370 reg = <0x18003000 0x4>;
371 mux-mask = <0x200>;
373 mdio@0 {
374 reg = <0x0>;
376 #size-cells = <0>;
380 reg = <0x10>;
382 #phy-cells = <0>;
389 reg = <0x18105000 0x1000>;
394 reg = <0x18008000 0x20>;
403 reg = <0x18009000 0x50>;
406 #size-cells = <0>;
413 ranges = <0 0x1800c000 0x1000>;
419 reg = <0x100 0x1a4>;
427 reg = <0x100 0x14>;
436 reg = <0x140 0x24>;
446 reg = <0x164 0x4>;
450 #phy-cells = <0>;
455 reg = <0x180 0x4>;
460 reg = <0x1c0 0x24>;
487 reg = <0x2c0 0x10>;
488 #thermal-sensor-cells = <0>;
495 reg = <0x18007000 0x1000>;
502 #size-cells = <0>;
508 reg = <0x18004000 0x14>;
513 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
518 #size-cells = <0>;
525 reg = <0x18029200 0x184>,
526 <0x18029000 0x124>,
527 <0x1811b408 0x004>,
528 <0x180293a0 0x01c>;
548 #size-cells = <0>;
550 spi_nor: flash@0 {
552 reg = <0>;
564 polling-delay-passive = <0>;
572 hysteresis = <0>;