Lines Matching +full:l2 +full:- +full:intc
2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
29 compatible = "arm,armv7-timer";
30 interrupt-parent = <&local_intc>;
35 always-on;
39 #address-cells = <1>;
40 #size-cells = <0>;
41 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
43 /* Source for d/i-cache-line-size and d/i-cache-sets
44 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
45 * /about-the-l1-memory-system?lang=en
47 * Source for d/i-cache-size
48 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
52 compatible = "arm,cortex-a53";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x0 0x000000d8>;
56 d-cache-size = <0x8000>;
57 d-cache-line-size = <64>;
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
62 next-level-cache = <&l2>;
67 compatible = "arm,cortex-a53";
69 enable-method = "spin-table";
70 cpu-release-addr = <0x0 0x000000e0>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
77 next-level-cache = <&l2>;
82 compatible = "arm,cortex-a53";
84 enable-method = "spin-table";
85 cpu-release-addr = <0x0 0x000000e8>;
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
92 next-level-cache = <&l2>;
97 compatible = "arm,cortex-a53";
99 enable-method = "spin-table";
100 cpu-release-addr = <0x0 0x000000f0>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
107 next-level-cache = <&l2>;
110 /* Source for cache-line-size + cache-sets
112 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
113 * Source for cache-size
114 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
116 l2: l2-cache0 { label
118 cache-size = <0x80000>;
119 cache-line-size = <64>;
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
121 cache-level = <2>;
126 /* Make the BCM2835-style global interrupt controller be a child of the
127 * CPU-local interrupt controller.
129 &intc {
130 compatible = "brcm,bcm2836-armctrl-ic";
132 interrupt-parent = <&local_intc>;
137 coefficients = <(-538) 412000>;
142 compatible = "brcm,bcm2837-thermal";