Lines Matching +full:soc +full:- +full:gpio53
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
34 soc {
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
116 reg-names = "pm", "asb", "rpivid_asb";
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00241011>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00241011>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00241011>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00241011>;
175 compatible = "brcm,bcm2835-spi";
179 #address-cells = <1>;
180 #size-cells = <0>;
185 compatible = "brcm,bcm2835-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 compatible = "brcm,bcm2835-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
205 compatible = "brcm,bcm2835-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "brcm,bcm2711-pixelvalve0";
262 compatible = "brcm,bcm2711-pixelvalve1";
269 compatible = "brcm,bcm2711-pixelvalve2";
276 compatible = "brcm,bcm2835-pwm";
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <2>;
286 compatible = "brcm,bcm2711-pixelvalve4";
293 compatible = "brcm,bcm2711-hvs";
299 compatible = "brcm,bcm2711-pixelvalve3";
306 compatible = "brcm,bcm2711-vec";
314 compatible = "brcm,brcm2711-dvp";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
330 compatible = "brcm,bcm2711-hdmi0";
340 reg-names = "hdmi",
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
371 compatible = "brcm,bcm2711-hdmi1";
381 reg-names = "hdmi",
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
413 * emmc2 has different DMA constraints based on SoC revisions. It was
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
427 compatible = "brcm,bcm2711-emmc2";
435 arm-pmu {
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
455 arm,cpu-registers-not-fw-configured;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
463 /* Source for d/i-cache-line-size and d/i-cache-sets
465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
466 * Source for d/i-cache-size
472 compatible = "arm,cortex-a72";
474 enable-method = "spin-table";
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
477 d-cache-line-size = <64>;
478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
479 i-cache-size = <0xc000>;
480 i-cache-line-size = <64>;
481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
482 next-level-cache = <&l2>;
487 compatible = "arm,cortex-a72";
489 enable-method = "spin-table";
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
492 d-cache-line-size = <64>;
493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
494 i-cache-size = <0xc000>;
495 i-cache-line-size = <64>;
496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
497 next-level-cache = <&l2>;
502 compatible = "arm,cortex-a72";
504 enable-method = "spin-table";
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
507 d-cache-line-size = <64>;
508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
509 i-cache-size = <0xc000>;
510 i-cache-line-size = <64>;
511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
512 next-level-cache = <&l2>;
517 compatible = "arm,cortex-a72";
519 enable-method = "spin-table";
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
522 d-cache-line-size = <64>;
523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
524 i-cache-size = <0xc000>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
527 next-level-cache = <&l2>;
530 /* Source for d/i-cache-line-size and d/i-cache-sets
532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
533 * Source for d/i-cache-size
537 l2: l2-cache0 {
539 cache-size = <0x100000>;
540 cache-line-size = <64>;
541 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
542 cache-level = <2>;
547 compatible = "simple-bus";
548 #address-cells = <2>;
549 #size-cells = <1>;
555 compatible = "brcm,bcm2711-pcie";
558 #address-cells = <3>;
559 #interrupt-cells = <1>;
560 #size-cells = <2>;
563 interrupt-names = "pcie", "msi";
564 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
565 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
573 msi-controller;
574 msi-parent = <&pcie0>;
583 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
585 brcm,enable-ssc;
589 compatible = "brcm,bcm2711-genet-v5";
591 #address-cells = <0x1>;
592 #size-cells = <0x1>;
598 compatible = "brcm,genet-mdio-v5";
600 reg-names = "mdio";
601 #address-cells = <0x1>;
602 #size-cells = <0x0>;
607 compatible = "brcm,2711-v3d";
610 reg-names = "hub", "core0";
612 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
620 clock-frequency = <54000000>;
624 compatible = "brcm,bcm2711-cprman";
628 coefficients = <(-487) 410040>;
629 thermal-sensors = <&thermal>;
638 compatible = "brcm,bcm2711-dsi1";
642 compatible = "brcm,bcm2711-gpio";
648 gpio-ranges = <&gpio 0 0 58>;
651 pin-gpclk {
654 bias-disable;
658 pin-gpclk {
661 bias-disable;
665 pin-gpclk {
668 bias-disable;
673 pin-sda {
676 bias-pull-up;
678 pin-scl {
681 bias-disable;
685 pin-sda {
688 bias-pull-up;
690 pin-scl {
693 bias-disable;
697 pin-sda {
700 bias-pull-up;
702 pin-scl {
705 bias-disable;
709 pin-sda {
712 bias-pull-up;
714 pin-scl {
717 bias-disable;
721 pin-sda {
724 bias-pull-up;
726 pin-scl {
729 bias-disable;
733 pin-sda {
736 bias-pull-up;
738 pin-scl {
741 bias-disable;
745 pin-sda {
748 bias-pull-up;
750 pin-scl {
753 bias-disable;
757 pin-sda {
760 bias-pull-up;
762 pin-scl {
765 bias-disable;
769 pin-sda {
772 bias-pull-up;
774 pin-scl {
777 bias-disable;
781 pin-sda {
784 bias-pull-up;
786 pin-scl {
789 bias-disable;
793 pins-i2c-slave {
803 pins-jtag {
809 "gpio53";
815 pins-mii {
824 pins-mii {
834 pins-pcm {
838 "gpio53";
844 pin-pwm {
847 bias-disable;
851 pin-pwm {
854 bias-disable;
858 pin-pwm {
861 bias-disable;
865 pin-pwm {
868 bias-disable;
872 pin-pwm {
875 bias-disable;
879 pin-pwm {
882 bias-disable;
886 pin-pwm {
889 bias-disable;
893 pin-pwm {
896 bias-disable;
900 pin-pwm {
901 pins = "gpio53";
903 bias-disable;
908 pin-start-stop {
912 pin-rx-ok {
918 pin-irq {
924 pin-irq {
930 pins-mdio {
937 pins-mdio {
945 pins-spi {
954 pins-spi {
964 pins-spi {
973 pins-spi {
982 pins-spi {
991 pins-spi {
1001 pin-tx {
1004 bias-disable;
1006 pin-rx {
1009 bias-pull-up;
1013 pin-cts {
1016 bias-pull-up;
1018 pin-rts {
1021 bias-disable;
1025 pin-tx {
1028 bias-disable;
1030 pin-rx {
1033 bias-pull-up;
1037 pin-cts {
1040 bias-pull-up;
1042 pin-rts {
1045 bias-disable;
1049 pin-tx {
1052 bias-disable;
1054 pin-rx {
1057 bias-pull-up;
1061 pin-cts {
1064 bias-pull-up;
1066 pin-rts {
1069 bias-disable;
1073 pin-tx {
1076 bias-disable;
1078 pin-rx {
1081 bias-pull-up;
1085 pin-cts {
1088 bias-pull-up;
1090 pin-rts {
1093 bias-disable;
1099 #address-cells = <2>;
1108 alloc-ranges = <0x0 0x00000000 0x40000000>;
1112 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1117 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1169 compatible = "brcm,bcm2711-vec";