Lines Matching +full:0 +full:x118
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
61 secondary-boot-reg = <0x35004178>;
70 secondary-boot-reg = <0x35004178>;
79 secondary-boot-reg = <0x35004178>;
88 ranges = <0 0x34000000 0x102f83ac>;
94 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
99 reg = <0x01001f00 0x24>;
104 reg = <0x01003000 0x524>;
118 reg = <0x01006000 0x1c>;
127 ranges = <0 0x3e000000 0x0001c070>;
131 uartb: serial@0 {
134 reg = <0x00000000 0x118>;
144 reg = <0x00001000 0x118>;
154 reg = <0x00002000 0x118>;
163 reg = <0x00016000 0x70>;
166 #size-cells = <0>;
173 reg = <0x00017000 0x70>;
176 #size-cells = <0>;
183 reg = <0x00018000 0x70>;
186 #size-cells = <0>;
193 reg = <0x0001c000 0x70>;
196 #size-cells = <0>;
205 ranges = <0 0x3e300000 0x01b77000>;
211 reg = <0x00e20000 0x10000>;
222 reg = <0x00e30000 0x28>;
223 #phy-cells = <0>;
229 reg = <0x00e80000 0x801c>;
237 reg = <0x00e90000 0x801c>;
245 reg = <0x00ea0000 0x801c>;
253 reg = <0x00eb0000 0x801c>;
261 reg = <0x01b0e000 0x78>;
267 #address-cells = <0>;
269 reg = <0x01b21000 0x1000>,
270 <0x01b22000 0x1000>;
285 #clock-cells = <0>;
291 #clock-cells = <0>;
297 #clock-cells = <0>;
303 #clock-cells = <0>;
309 #clock-cells = <0>;
315 #clock-cells = <0>;
321 #clock-cells = <0>;
327 #clock-cells = <0>;
333 #clock-cells = <0>;
339 #clock-cells = <0>;
345 #clock-cells = <0>;
351 #clock-cells = <0>;
357 #clock-cells = <0>;
363 #clock-cells = <0>;
369 #clock-cells = <0>;
376 reg = <0x35001000 0x0f00>;
383 reg = <0x35002000 0x0f00>;
390 reg = <0x3e011000 0x0f00>;
403 reg = <0x3f001000 0x0f00>;